APB Interface Clock
The APB programming interface is clocked by the PMC_LSBUS_CLK clock.
AXI Interface Clock
The AXI DMA interface is clocked by the PMC_IRO_CLK clock. These clocks are shared with other functional units.
Reference Clock
The controller logic itself is clocked by the QSPI reference clock, which includes the DLL for the I/O clock. The reference clock is generated by the PMC clock controller using the CRP register set.
- OSPI_REF_CLK clock frequency is controlled by the CRP OSPI_REF_CTRL register
Resets
The controller has two resets. The controller reset, OSPI_RESET, comes from the PMC reset controller. This signal asserts when software writes to the RST_OSPI register or by any one of a number of system-level resets described in the keyref="exs1538423965644"/> chapter.
The controller also has a separate PHY reset for the DLL. This is controlled by the PHY_Config register.
Asserting Reset
Resets should only be asserted when the controller is inactive, [IDLE] = 1. Doing so at other times produces unknown results.
Reset Condition
The following states are set by the controller reset:
- Transactions on the I/O interface are abruptly terminated (must be avoided, check [IDLE] to confirm the I/O is quiescent)
- Pending requests from the software are canceled
- All registers are set to their reset value
System Interrupt
OSPI has one system interrupt signal. The system interrupt can be asserted by any one of the three interrupt status registers contained with the OSPI registers set.
- Controller interrupt register: OSPI.IRQ_Status
- DMA source interrupt register: OSPI.DMA_SRC_ISR
- DMA destination interrupt register: OSPI.DMA_DST_ISR
The system interrupt is routed to several places as described in System Interrupts.
System Error
The APB programming interface can generate an address decode error if it detects a software access violation. The error signal is routed to the system error accumulator for processing as described in System Errors.