APB Interface
The single APB programming interface provides access to the read/write control and status registers, and the transmit and receive FIFOs. The APB interface is connected to the LPD IOP switch and is used for all controller configuration, control, and data transfer operations.
Clocks
UART system signals are described in this section.
The UART system clocks include:
- LPD_LSBUS_CLK for the APB programming interface
- UARTx_REF_CLK for the controller logic
Both of these clocks always come from the LPD clock and reset controlled by the CRL register module: LPD_LSBUS_CTRL and UARTx_REF_CTRL registers.
System Reset
The UART controller is reset by a system reset, a POR reset, or an individual software reset controlled by the CRL register module: RST_UARTx [RESET].
The controller registers are reset; this disables the controller, deasserts error and interrupt signals, clears the FIFO pointers, sets default configurations, and more. Refer to the reset value in the register reference document.
System Interrupt
Each UART generates a system interrupt. The IRQs are listed in the System Interrupts Table section.
The system interrupt is an OR of the 11 events listed in the interrupt status register.
The controller system interrupt is listed in System Interrupts table.
APB Decode Error
The APB programming interface generates an address decode error if it detects an address out of range.
If an APB offset address above 0xFFF is detected, then an out of range address condition occurs. This causes the APB address decode error interrupt status bit to be set; refer to the LPD_IOP_SLCR.APB_ISR register.
The controller can also assert the APB bus error signal back to the interconnect. The bus error signal can be enabled using the LPD_IOP_SLCR.APB_CTRL register.
APB Parity Error
The APB programming interface can detect a parity error in the address or write data. Parity error is sent to the LPD_IOP_SLCR.PARITY_ISR register.