System Signals - AM011

Clocks

The Accelerator RAM has one main clock that is driven by an output from the clock and reset unit in the PMC (CRP) or by the PL. This is dependent on the setting of the MAIN_CLK (XRAM_SLCR) register. This clock is used by the crossbar switch, the XMPUs, and the memory banks.

Resets

Reset can always be from the CRL module with an option to reset from the PL.

The Accelerator RAM can be toggled in-and-out of reset or held in reset until a POR occurs using the CRL.RST_XRAM register.

System Interrupts

The system interrupt signals go to the GICs, PSM interrupt controller, and the PL. The Accelerator RAM interrupts are included in a table in the System Interrupts chapter.

System Errors

The system error signals go to the PMC EAM and the PL. The Accelerator RAM errors are included in a table in the System Errors chapter.

PL access to Accelerator RAM clocks, resets, interrupts, and errors is only supported in devices that support the PL interface to the Accelerator RAM. See Devices with Accelerator RAM and Access Ports.