Memory transaction requests from the processors and DMA units in the SoC will normally go directly to the DDR memory controllers via the NoC interconnect. Many of them can be routed to go the system memory management unit (SMMU). The route through the SMMU includes a 48-bit virtual address on the input that is translated to a 44-bit physical address. The transactions go to the cache coherent interconnect (CCI); if the transaction is marked a coherent, then the physical address is looked up in the system L2 caches. The CCI requires the cache signals to be valid because the system cache must decide how to handle the transaction I/O coherency. Coherency checking can be disabled by declaring the transaction as non-cacheable in AxCACHE. In this case, the transaction flows through the CCI without disturbing the L2 cache.
Cache transaction are identified using the four AxCACHE bits. The encoding is shown in the AxCACHE section. In some cases, the host generates these four bits on a per transaction basis. In other cases, the AxCACHE bits are defined by register settings. In this situation, a register write is required to switch a host between coherent and non-coherent transactions.