System Interrupts

The following table lists the system interrupts.

Table 1. System Interrupts
Name	Description and Source	IRQ	PMC & PSM Global Register	PS9 Port	CIPS Signal
reserved	reserved	32:39	GICP0 [0:7]
RPU0_PERF_MON	RPU 0 performance monitor	40	GICP0 [8]	ps_pl_irq_lpd[8]	PS_PL_IRQ_LPD_interrupt0
RPU1_PERF_MON	RPU 1 performance monitor	41	GICP0 [9]	ps_pl_irq_lpd[9]	PS_PL_IRQ_LPD_interrupt1
OCM	OCM error	42	GICP0 [10]	ps_pl_irq_lpd[10]	PS_PL_IRQ_LPD_interrupt2
RPU0_ERR	RPU 0 combined errors: FPU, memory ECC, and AXI access	43	GICP0 [11]	ps_pl_irq_lpd[11]	PS_PL_IRQ_LPD_interrupt3
RPU1_ERR	RPU 1 combined errors: FPU, memory ECC, and AXI access	44	GICP0 [12]	ps_pl_irq_lpd[12]	PS_PL_IRQ_LPD_interrupt4
LPD_GPIO	LPD GPIO controller	45	GICP0 [13]	ps_pl_irq_lpd[13]	PS_PL_IRQ_LPD_interrupt5
LPD_I2C0	LPD I2C 0 controller	46	GICP0 [14]	ps_pl_irq_lpd[14]	PS_PL_IRQ_LPD_interrupt6
LPD_I2C1	LPD I2C 1 controller	47	GICP0 [15]	ps_pl_irq_lpd[15]	PS_PL_IRQ_LPD_interrupt7
SPI0	SPI 0 controller	48	GICP0 [16]	ps_pl_irq_lpd[16]	PS_PL_IRQ_LPD_interrupt8
SPI1	SPI 1 controller	49	GICP0 [17]	ps_pl_irq_lpd[17]	PS_PL_IRQ_LPD_interrupt9
UART0	UART 0 controller	50	GICP0 [18]	ps_pl_irq_lpd[18]	PS_PL_IRQ_LPD_interrupt10
UART1	UART 1 controller	51	GICP0 [19]	ps_pl_irq_lpd[19]	PS_PL_IRQ_LPD_interrupt11
CANFD0	CANFD 0 controller	52	GICP0 [20]	ps_pl_irq_lpd[20]	PS_PL_IRQ_LPD_interrupt12
CANFD1	CANFD 1 controller	53	GICP0 [21]	ps_pl_irq_lpd[21]	PS_PL_IRQ_LPD_interrupt13
USB_INTR	USB 2.0 controller bulk transfer, isochronous transfer, controller interrupt, control transfer	54:57	GICP0 [22:25]	ps_pl_irq_lpd[22:25]	PS_PL_IRQ_LPD_interrupt14[0:3]
USB_Controller	USB 2.0 controller	58	GICP0 [26]	ps_pl_irq_lpd[26]	PS_PL_IRQ_LPD_interrupt15
PMC_BUF_IPI	OR of all IPIs targeted to PMC with message buffer	59	GICP0 [27]	ps_pl_irq_lpd[27]	PS_PL_IRQ_LPD_interrupt16
PMC_NOBUF_IPI	OR of all IPIs targeted to PMC without message buffer	60	GICP0 [28]	ps_pl_irq_lpd[28]	PS_PL_IRQ_LPD_interrupt17
PSM_IPI	OR of all IPIs targeted to PSM	61	GICP0 [29]	ps_pl_irq_lpd[29]	PS_PL_IRQ_LPD_interrupt18
IPI0	IPI 0 interrupt	62	GICP0 [30]	ps_pl_irq_lpd[30]	PS_PL_IRQ_LPD_interrupt19
IPI1	IPI 1 interrupt	63	GICP0 [31]	ps_pl_irq_lpd[31]	PS_PL_IRQ_LPD_interrupt20
IPI2	IPI 2 interrupt	64	GICP1 [0]	ps_pl_irq_lpd[32]	PS_PL_IRQ_LPD_interrupt21
IPI3	IPI 3 interrupt	65	GICP1 [1]	ps_pl_irq_lpd[33]	PS_PL_IRQ_LPD_interrupt22
IPI4	IPI 4 interrupt	66	GICP1 [2]	ps_pl_irq_lpd[34]	PS_PL_IRQ_LPD_interrupt23
IPI5	IPI 5 interrupt	67	GICP1 [3]	ps_pl_irq_lpd[35]	PS_PL_IRQ_LPD_interrupt24
IPI6	IPI 6 interrupt	68	GICP1 [4]	ps_pl_irq_lpd[36]	PS_PL_IRQ_LPD_interrupt25
TTC0_Timer[1:3]	TTC controller 0, timer/counter 1 to 3	69:71	GICP1 [5:7]	ps_pl_irq_lpd[37:39]	PS_PL_IRQ_LPD_interrupt26[0:2]
TTC1_Timer[1:3]	TTC controller 1, timer/counter 1 to 3	72:74	GICP1 [8:10]	ps_pl_irq_lpd[40:42]	PS_PL_IRQ_LPD_interrupt27[0:2]
TTC2_Timer[1:3]	TTC controller 2, timer/counter 1 to 3	75:77	GICP1 [11:13]	ps_pl_irq_lpd[43:45]	PS_PL_IRQ_LPD_interrupt28[0:2]
TTC3_Timer[1:3]	TTC controller 3, timer/counter 1 to 3	78:80	GICP1 [14:16]	ps_pl_irq_lpd[46:48]	PS_PL_IRQ_LPD_interrupt29[0:2]
LPD_SWDT_INT	SWDT in LPD	81	GICP1 [17]	ps_pl_irq_lpd[49]	PS_PL_IRQ_LPD_interrupt30
PSM	PSM interrupt	82	GICP1 [18]	ps_pl_irq_lpd[50]	PS_PL_IRQ_LPD_interrupt31
LPD_XPPU	XPPU in LPD	83	GICP1 [19]	ps_pl_irq_lpd[51]	PS_PL_IRQ_LPD_interrupt32
LPD_INT	OR of peripherals on the LPD interconnect	84	GICP1 [20]	ps_pl_irq_lpd[52]	PS_PL_IRQ_LPD_interrupt33
PMC_SysMon	PMC system monitor	85	GICP1 [21]	ps_pl_irq_lpd[53]	PS_PL_IRQ_LPD_interrupt34
reserved	reserved	86:87	GICP1 [22:23]
GEM0	GEM controller 0	88	GICP1 [24]	ps_pl_irq_lpd[56]	PS_PL_IRQ_LPD_interrupt35
GEM0_Wakeup	GEM controller 0 wake-up	89	GICP1 [25]	ps_pl_irq_lpd[57]	PS_PL_IRQ_LPD_interrupt36
GEM1	GEM controller 1	90	GICP1 [26]	ps_pl_irq_lpd[58]	PS_PL_IRQ_LPD_interrupt37
GEM1_Wakeup	GEM controller 1 wake-up	91	GICP1 [27]	ps_pl_irq_lpd[59]	PS_PL_IRQ_LPD_interrupt38
LPD_DMA[0:3]	LPD DMA channels 0 to 3	92:95	GICP1 [28:31]	ps_pl_irq_lpd[60:63]	PS_PL_IRQ_LPD_interrupt39[0:3]
LPD_DMA[4:7]	LPD DMA channels 4 to 7	96:99	GICP2 [0:3]	ps_pl_irq_lpd[64:67]	PS_PL_IRQ_LPD_interrupt39[4:7]
OCM_XMPU	XMPU for the OCM	100	GICP2 [4]	ps_pl_irq_lpd[68]	PS_PL_IRQ_LPD_interrupt40
LPD_SWDT_INT_PEND	SWDT in LPD reset pending	101	GICP2 [5]	ps_pl_irq_lpd[69]	PS_PL_IRQ_LPD_interrupt41
LPD_SWDT_INT_WS[0]	SWDT in LPD WS 0	102	GICP2 [6]	ps_pl_irq_lpd[70]	PS_PL_IRQ_LPD_interrupt42
LPD_SWDT_INT_WS[1]	SWDT in LPD WS 1	103	GICP2 [7]	ps_pl_irq_lpd[71]	PS_PL_IRQ_LPD_interrupt43
CPM	OR of CPM interrupts and events	104	GICP2 [8]
CPM_CE	CPM interrupt 1, correctable error	105	GICP2 [9]
USB_PME	USB power management event (PME) from the USB power management unit (PMU)	106	GICP2 [10]	ps_pl_irq_lpd[74]	PS_PL_IRQ_LPD_interrupt46
CPM_UE	CPM interrupt 2, uncorrectable error	107	GICP2 [11]
reserved	reserved	108:109	GICP2 [12:13]
XRAM	Accelerator RAM controller	110	GICP2 [14]	ps_pl_irq_lpd[78]	PS_PL_IRQ_LPD_interrupt48
XRAM_CE	Accelerator RAM correctable error	111	GICP2 [15]
XRAM_UE	Accelerator RAM uncorrectable error	112	GICP2 [16]	ps_pl_irq_lpd[79]	PS_PL_IRQ_LPD_interrupt49
reserved	reserved	113:115	GICP2 [17:19]	ps_pl_irq_fpd[8]	PS_PL_IRQ_FPD_interrupt0
PL_PS_Group0_[0:7]	PL_IRQ[0:7] to LPD	116:123	GICP2 [20:27]	ps_pl_irq_fpd[9]	PS_PL_IRQ_FPD_interrupt1
PL_PS_Group1_[0:3]	PL_IRQ[8:11] to FPD	124:127	GICP2 [28:31]	ps_pl_irq_fpd[10]	PS_PL_IRQ_FPD_interrupt2
PL_PS_Group1_[4:7]	PL_IRQ[12:15] to FPD	128:131	GICP3 [0:3]	ps_pl_irq_fpd[11]	PS_PL_IRQ_FPD_interrupt3
FPD_SWDT_INT	SWDT in FPD	132	GICP3 [4]	ps_pl_irq_fpd[12]	PS_PL_IRQ_FPD_interrupt4
reserved	reserved	133	GICP3 [5]	ps_pl_irq_fpd[13]	PS_PL_IRQ_FPD_interrupt5
FPD_XMPU	XMPU in FPD	134	GICP3 [6]	ps_pl_irq_fpd[14]	PS_PL_IRQ_FPD_interrupt6
APU_L2	APU L2-cache double bit ECC error	135	GICP3 [7]	ps_pl_irq_fpd[15]	PS_PL_IRQ_FPD_interrupt7
EXT_ERR	External error	136	GICP3 [8]	ps_pl_irq_fpd[16]	PS_PL_IRQ_FPD_interrupt8
APU processor	APU interrupts	137	GICP3 [9]	ps_pl_irq_fpd[17]	PS_PL_IRQ_FPD_interrupt9
CCI	FPD cache coherent interconnect (CCI)	138	GICP3 [10]	ps_pl_irq_fpd[18]	PS_PL_IRQ_FPD_interrupt10
FPD_SMMU	FPD system memory management unit (SMMU)	139	GICP3 [11]
FPD_SWDT_INT_WS0	SWDT controller in FPD, WS0	140	GICP3 [12]
FPD_SWDT_INT_RST_PEND	FPD_SWDT reset pending	141	GICP3 [13]
FPD_SWDT_INT_WS1	SWDT controller in FPD, WS1	142	GICP3 [14]
reserved	reserved	143:151	GICP3 [15:23]
PMC_CFU	Configuration frames unit	152	GICP3 [24]	ps_pl_irq_pmc[0]	PS_PL_IRQ_PMC_interrupt0
reserved	reserved	153	GICP3 [25]
PMC_GPIO	PMC GPIO controller	154	GICP3 [26]	ps_pl_irq_pmc[2]	PS_PL_IRQ_PMC_interrupt2
PMC_I2C	PMC I2C controller	155	GICP3 [27]	ps_pl_irq_pmc[3]	PS_PL_IRQ_PMC_interrupt3
OSPI	OSPI controller	156	GICP3 [28]	ps_pl_irq_pmc[4]	PS_PL_IRQ_PMC_interrupt4
QSPI	QSPI controller	157	GICP3 [29]	ps_pl_irq_pmc[5]	PS_PL_IRQ_PMC_interrupt5
SD/eMMC0	SD/eMMC controller 0	158	GICP3 [30]	ps_pl_irq_pmc[6]	PS_PL_IRQ_PMC_interrupt6
SD/eMMC0_Wakeup	SD controller 0 wake-up	159	GICP3 [31]	ps_pl_irq_pmc[7]	PS_PL_IRQ_PMC_interrupt7
SD/eMMC1	SD/eMMC controller 1	160	GICP4[0]	ps_pl_irq_pmc[8]	PS_PL_IRQ_PMC_interrupt8
SD/eMMC1_Wakeup	SD controller 1 wake-up	161	GICP4[1]	ps_pl_irq_pmc[9]	PS_PL_IRQ_PMC_interrupt9
reserved	reserved	162	GICP4[2]
PMC_DMA0	PMC DMA 0	163	GICP4[3]	ps_pl_irq_pmc[11]	PS_PL_IRQ_PMC_interrupt11
PMC_DMA1	PMC DMA 1	164	GICP4[4]	ps_pl_irq_pmc[12]	PS_PL_IRQ_PMC_interrupt12
PMC_AXI	OR of the peripherals on PMC interconnect	165	GICP4[5]	ps_pl_irq_pmc[13]	PS_PL_IRQ_PMC_interrupt13
PMC_XPPU	PMC XPPU	166	GICP4[6]	ps_pl_irq_pmc[14]	PS_PL_IRQ_PMC_interrupt14
PMC_XMPU	PMC XMPU	167	GICP4[7]	ps_pl_irq_pmc[15]	PS_PL_IRQ_PMC_interrupt15
SBI	Supervised boot interface unit	168	GICP4[8]	ps_pl_irq_pmc[16]	PS_PL_IRQ_PMC_interrupt16
AES	AES	169	GICP4[9]	ps_pl_irq_pmc[17]	PS_PL_IRQ_PMC_interrupt17
RSA_ECC	RSA/ECC	170	GICP4[10]	ps_pl_irq_pmc[18]	PS_PL_IRQ_PMC_interrupt18
EFUSE	eFUSE	171	GICP4[11]	ps_pl_irq_pmc[19]	PS_PL_IRQ_PMC_interrupt19
SHA	SHA	172	GICP4[12]	ps_pl_irq_pmc[20]	PS_PL_IRQ_PMC_interrupt20
TRNG	True random number generator	173	GICP4[13]	ps_pl_irq_pmc[21]	PS_PL_IRQ_PMC_interrupt21
RTC_Alarm	RTC alarm	174	GICP4[14]	ps_pl_irq_pmc[22]	PS_PL_IRQ_PMC_interrupt22
RTC_Seconds	RTC seconds	175	GICP4[15]	ps_pl_irq_pmc[23]	PS_PL_IRQ_PMC_interrupt23
SYSMON	Voltage and temperature system monitor	176	GICP4[16]	ps_pl_irq_pmc[24:25]	PS_PL_IRQ_PMC_interrupt24[0:1]
reserved	reserved	177	GICP4[17]
NPI_IRQ0	NPI interrupt 0, DDRMC_MB all correctable software errors and interrupts	178	GICP4[18]	ps_pl_irq_pmc[26]	PS_PL_IRQ_PMC_interrupt25[0]
NPI_IRQ2	NPI interrupt 2, DDRMC_MC all correctable errors	179	GICP4[19]	ps_pl_irq_pmc[27]	PS_PL_IRQ_PMC_interrupt25[1]
NPI_IRQ5	NPI interrupt 5, AI Engine all correctable errors and miscellaneous events	180	GICP4[20]	ps_pl_irq_pmc[28]	PS_PL_IRQ_PMC_interrupt25[2]
NPI_IRQ6	NPI interrupt 6, AI Engine debug events and miscellaneous events	181	GICP4[21]	ps_pl_irq_pmc[29]	PS_PL_IRQ_PMC_interrupt25[3]
NPI_IRQ7	NPI interrupt 7, AI Engine miscellaneous events	182	GICP4[22]	ps_pl_irq_pmc[30]	PS_PL_IRQ_PMC_interrupt25[4]
NPI_IRQ8	NPI interrupt 8, GT interrupts and requests	183	GICP4[23]	ps_pl_irq_pmc[31]	PS_PL_IRQ_PMC_interrupt25[5]
NPI_IRQ9	NPI interrupt 9, GT all correctable errors	184	GICP4[24]	ps_pl_irq_pmc[32]	PS_PL_IRQ_PMC_interrupt25[6]
reserved	reserved	185	GICP4[25]
NPI_IRQ20	NPI interrupt 20, NoC user interrupts and errors	186	GICP4[26]	ps_pl_irq_pmc[34]	PS_PL_IRQ_PMC_interrupt25[8]
NPI_IRQ21	NPI interrupt 21, NoC user interrupts and errors	187	GICP4[27]	ps_pl_irq_pmc[35]	PS_PL_IRQ_PMC_interrupt25[9]
NPI_IRQ22	NPI interrupt 22, NoC user interrupts and errors	188	GICP4[28]	ps_pl_irq_pmc[36]	PS_PL_IRQ_PMC_interrupt25[10]
NPI_IRQ23	NPI interrupt 23, NoC user interrupts and errors	189	GICP4[29]	ps_pl_irq_pmc[37]	PS_PL_IRQ_PMC_interrupt25[11]
PMC RAM	PMC RAM	190	GICP4[30]	ps_pl_irq_pmc[38]	PS_PL_IRQ_PMC_interrupt26
reserved	reserved	191	GICP4[31]

System Interrupts - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)