The following table lists the system errors routed to the PMC system error accumulator module (EAM).
Error Name | SW Error Number | PMC Global Register | JTAG Error Bit | Description |
---|---|---|---|---|
reserved | 0x00 | PMC_ERR1_STATUS[0] | 63 | reserved |
BootROM NCR | 0x01 | PMC_ERR1_STATUS[1] | 62 | BootROM non-correctable error; set during boot |
PLM CR | 0x02 | PMC_ERR1_STATUS[2] | 61 | PLM boot correctable error; set during boot. See PMC_GLOBAL.PLM_FW_ERR register. |
PLM NCR | 0x03 | PMC_ERR1_STATUS[3] | 60 | PLM boot non-correctable error; set during boot. See PMC_GLOBAL.PLM_FW_ERR register. |
GSW CR | 0x04 | PMC_ERR1_STATUS[4] | 59 | General software correctable error; set by any processor after boot |
GSW NCR | 0x05 | PMC_ERR1_STATUS[5] | 58 | General software non-correctable error; set by any processor after boot |
CFU | 0x06 | PMC_ERR1_STATUS[6] | 57 | CFU error |
CFRAME | 0x07 | PMC_ERR1_STATUS[7] | 56 | CFRAME error |
PSM CR | 0x08 | PMC_ERR1_STATUS[8] | 55 | PSM correctable error |
PSM NCR | 0x09 | PMC_ERR1_STATUS[9] | 54 | PSM non-correctable error |
DDRMC MB CR | 0x0A | PMC_ERR1_STATUS[10] | 53 | DDRMC MicroBlazeâ„¢ correctable ECC |
DDRMC MB NCR | 0x0B | PMC_ERR1_STATUS[11] | 52 | DDRMC MicroBlaze non-correctable ECC |
NOC CR | 0x0C | PMC_ERR1_STATUS[12] | 51 | NoC correctable error |
NOC NCR | 0x0D | PMC_ERR1_STATUS[13] | 50 | NoC non-correctable error |
NOC user | 0x0E | PMC_ERR1_STATUS[14] | 49 | NoC user error |
MMCM lock | 0x0F | PMC_ERR1_STATUS[15] | 48 | MMCM lock error |
AI Engine CR | 0x010 | PMC_ERR1_STATUS[16] | 47 | AI Engine correctable error |
AI Engine NCR | 0x011 | PMC_ERR1_STATUS[17] | 46 | AI Engine non-correctable error |
DDRMC MC ECC CR | 0x012 | PMC_ERR1_STATUS[18] | 45 | DDRMC memory correctable ECC |
DDRMC MC ECC NCR | 0x013 | PMC_ERR1_STATUS[19] | 44 | DDRMC memory non-correctable ECC |
GT CR | 0x014 | PMC_ERR1_STATUS[20] | 43 | GT correctable error |
GT NCR | 0x015 | PMC_ERR1_STATUS[21] | 42 | GT non-correctable error |
SYSMON CR | 0x016 | PMC_ERR1_STATUS[22] | 41 | System monitor correctable error |
SYSMON NCR | 0x017 | PMC_ERR1_STATUS[23] | 40 | System monitor non-correctable error |
User PL0 | 0x018 | PMC_ERR1_STATUS[24] | 39 | User-defined PL error |
User PL1 | 0x019 | PMC_ERR1_STATUS[25] | 38 | User-defined PL error |
User PL2 | 0x01A | PMC_ERR1_STATUS[26] | 37 | User-defined PL error |
User PL3 | 0x01B | PMC_ERR1_STATUS[27] | 36 | User-defined PL error |
NPI module | 0x01C | PMC_ERR1_STATUS[28] | 35 | NPI Module reported error |
SSIT Error 3 |
0x01D |
PMC_ERR1_STATUS[29] |
34 |
Stacked silicon integrated technology with super logic regions (SLR) errors |
PMC APB | 0x020 | PMC_ERR2_STATUS[0] | 31 |
General purpose PMC error, can be triggered by any of the following peripherals: * PMC Global Registers * PMC Clock & Reset (CRP) * PMC IOU Secure SLCR * PMC IOU SLCR * BBRAM Controller * PMC Analog Control Registers * RTC Control Registers |
PMC BootROM | 0x021 | PMC_ERR2_STATUS[1] | 30 | BootROM validation error |
RCU hardware | 0x022 | PMC_ERR2_STATUS[2] | 29 | RCU hardware error |
PPU hardware | 0x023 | PMC_ERR2_STATUS[3] | 28 | PPU hardware error |
PMC parity | 0x024 | PMC_ERR2_STATUS[4] | 27 | PMC main and IOP interconnect parity errors |
PMC CR | 0x025 | PMC_ERR2_STATUS[5] | 26 |
RCU and PPU correctable RAM errors: |
PMC NCR | 0x026 | PMC_ERR2_STATUS[6] | 25 | RCU and PPU non-correctable RAM error |
PMC SYSMON voltage |
0x027 |
PMC_ERR2_STATUS[7] |
24 |
Remote system monitor (SYSMON) voltage alarms: |
reserved |
0x02C |
PMC_ERR2_STATUS[12] |
19 |
reserved |
PMC SYSMON temperature |
0x02F |
PMC_ERR2_STATUS[15] |
16 |
Remote system monitor (SYSMON) temperature alarms: |
CFI NCR | 0x031 | PMC_ERR2_STATUS[17] | 14 |
CFI non-correctable error |
SEU CRC | 0x032 | PMC_ERR2_STATUS[18] | 13 | CFRAME SEU CRC error |
SEU ECC | 0x033 | PMC_ERR2_STATUS[19] | 12 | CFRAME SEU ECC error |
reserved | 0x034 | PMC_ERR2_STATUS[20] | 11 | reserved, returns 0 |
reserved | 0x035 | PMC_ERR2_STATUS[21] | 10 | reserved, returns 1 |
RTC alarm | 0x036 | PMC_ERR2_STATUS[22] | 9 | RTC alarm error |
NPLL | 0x037 | PMC_ERR2_STATUS[23] | 8 | PMC NPLL lock error; asserted while locking or when lock is lost |
PPLL | 0x038 | PMC_ERR2_STATUS[24] | 7 | PMC PPLL lock error; asserted while locking or when lock is lost |
Clock monitor | 0x039 | PMC_ERR2_STATUS[25] | 6 | PMC clock monitor (ClkMon) error signal driven by CRP.CLKMON_ISR.status register |
PMC timeout | 0x03A | PMC_ERR2_STATUS[26] | 5 | PMC interconnect switch timeout errors; from mission and timeout interrupt status registers in ePorts |
PMC XMPU | 0x03B | PMC_ERR2_STATUS[27] | 4 | PMC_XMPU error detection signal; includes read permission, write permission, and security access violations |
PMC XPPU | 0x03C | PMC_ERR2_STATUS[28] | 3 | PMC XPPU error detection; includes SMID not found, SMID parity error, read permission, SMID access, and TrustZone access violations |
SSIT error 0 |
0x03D |
PMC_ERR2_STATUS[29] |
2 |
Stacked silicon interconnect technology SLR errors; from SSI technology super logic regions 0 to 2 |