The processing system (PS) provides general-purpose, high-performance compute power with familiar operating environments. It includes the multicore application processing unit (APU) subsystem and the multicore real-time processing unit (RPU) subsystem. Linux and bare-metal software stacks can execute in the APU and RPU in a homogeneous or a heterogeneous environment.
The PMC subsystem provides device boot and management functions with its RCU BootROM code unit and the platform loader and management (PLM) firmware running in the PMC's PPU processor.
The device also includes a NoC interconnect, multiple DDR memory controllers, the PL, and integrated peripherals.
For software topics, refer to the Software Programming chapter.
Application Processing Unit
The APU subsystem is tightly coupled to a coherent interconnect with system cache to provide high-performance software compute power. The APU is located in the full-power domain (FPD). The APU can be used for computations, control-plane applications, operating systems, communications interfaces, and more.
The APU is based on two Arm® Cortex®-A72 CPU cores that include the Arm A64 instruction set in the v8-A architecture. The APU is tightly coupled to the cache coherent interconnect (CCI) that is surrounded by a system memory management unit (SMMU) for other transaction hosts including DMA units and other system processors. The CCI includes the L2 system cache memory with ECC to form a tightly-coupled coherent system. The APU includes the Arm generic interrupt controller (GIC-500) to manage shared and system interrupts.
Real-time Processing Unit
The RPU provides predictable software execution times for real-time applications.
The RPU processor is based on two Arm Cortex-R5F CPU cores that can operate in dual or lockstep mode. Each CPU includes separate L1 instruction and data caches and TCMs that are dedicated to their RPU cores to narrow down the deterministic behavior for real-time data processing applications. The CPUs feature out-of-order execution that is coupled with a single/double precision floating point unit (FPU). The processor also includes a general interrupt controller (GIC PL-390) to manage shared and system interrupts.
The RPU subsystem includes tightly-coupled memories (TCMs) and is placed close to the on-chip memory (OCM) for deterministic software execution rates in a standard programming environment. System memory space is cacheable, but the TCM and OCM memory spaces are non-cacheable. The RPU, TCMs, and OCM are located in the low-power domain (LPD).
NoC Interconnect
The NoC interconnect is pervasive across the device to connect the APU, RPU, and other processors to the DDR memory controllers and other functionality in and around the programmable logic.
DDR Memory Controller
The device includes one or more DDR4/LPDDR4 memory controllers that is accessible via the NoC.
High-bandwidth Memory Interface
Some devices include one or more high-bandwidth memory (HBM) interfaces that attach to the NoC interconnect and drive I/O buffers to the HBM die within the device. See High-Bandwidth Memory Interface.
Platform Management Controller
The PMC includes a ROM code unit (RCU) processor, the platform processing unit (PPU) that runs the platform loader and manager (PLM) firmware, the boot interfaces, and the voltage/temperature system monitor (SYSMON).
- ROM Code Unit
- The RCU processor executes the BootROM code to provide hardware boot. The BootROM code is the first to run after a device-level reset; this can include a power-on reset or software reset. The BootROM code initializes the device, enables the boot interface, and processes the boot header. To finish the hardware boot process, the RCU loads the PLM firmware into the PMC microprocessor and relinquishes control of the system to the PLM. After the PLM takes system control, the RCU switches to a services mode, which includes system monitoring and service execution including in-place PLM firmware update.
- Platform Loader and Manager Firmware
- The PLM firmware performs several tasks that include device configuration and partial-reconfiguration of the programmable logic. The PLM firmware loads the [vk]Processing System Manager (PSM) firmware to monitor the activity of the processing system.
- Boot Interfaces
- The boot interfaces include those for flash memory controllers for autonomous boot modes and the select map and JTAG boot interface for managed boot modes.
- Voltage and Temperature System Monitor
- The voltage and temperatures in the SoC are measured by the system monitors (SYSMON). Various voltage rails are monitored to detect out of range measurements for safety and anomalies for security. It also monitors under and over temperature conditions.
- Security Features
- The PMC includes an AES accelerator with GCM modes, SHA2, SHA3, public key cryptographic algorithms RSA with elliptic curve cryptography (ECC), true random number generator (TRNG), a physically unclonable function (PUF) to create a signature, and a public key infrastructure accelerator.
Security Documentation
For additional details, see the Versal Adaptive SoC Security Manual (UG1508).
This manual requires an active NDA to download from the Design Security Lounge.
Processing System Manager
The processing system manager (PSM) processor executes PSM firmware to manage and monitor the RPU and APU processing system subsystems. The PSM includes a system interrupt controller and an error accumulation module (EAM).
Programmable Logic
The PL is a scalable structure that provides the ability to create many possible functions. The integrated hardware options have interconnect interfaces and connections to the PL. The PL I/O includes both LVCMOS buffers and gigabit transceivers that cover a wide range of applications and frequencies. For more information, see the Programmable Logic section.
The programmable logic supports AXI SmartConnect core functionality that can be instantiated using a library of AMD LogiCORE™ IPs. The AXI SmartConnect core can be independent within the PL or extended and attached to the processing system through several AXI interfaces with and without coherency with the APU system cache.
Integrated Hardware Options
- Scalable AI Engine versions
- 4 MB Accelerator RAM (XRAM)
-
PL High-speed Connectivity
- Ethernet MACs, Interlaken
- Video decoder unit
- High-speed crypto engine
Coherent Module with PCIe
The coherent module with PCIe (CPM) interconnect is a device option that provides coherency between the PCIe controllers, a PL processor, and the PS. The CCIX interconnect adds memory coherency with external devices over PCIe. There are multiple types of CPM modules:
- CPM4 with PCIe 4.0 and CCIX 1.0 interconnect (device option in Versal adaptive SoC)
- CPM5 with PCIe 5.0 and CCIX 1.1 interconnect (device option in Versal adaptive SoC)
See Integrated Hardware Device Options for more information.
Power Domains
The device includes several power domains that are described in the Power chapter. The PMC power domain is required to boot, manage the device, and access the PMC I/O peripherals and flash memory controllers. The LPD is required for running the RPU. The FPD is required for the APU, the system caches, and the memory coherency subsystem. The SoC power domain (SPD) is for the NoC interconnect and DDR memory controllers. The PL power domain is for logic instantiated in the PL and also the integrated logic and peripherals. See the Power chapter for information on usages and restrictions.