The following table shows the SPI controller implementation.
| Device Generation | Instances | SPI Controller |
|---|---|---|
| AMD UltraScale+™ MPSoC | 2x in LPD on MIO pins | Cadence version r109 |
| AMD Versal™ adaptive SoC | 2x in LPD on MIO pins | Cadence version r112 |
The following table shows the SPI controller implementation.
| Device Generation | Instances | SPI Controller |
|---|---|---|
| AMD UltraScale+™ MPSoC | 2x in LPD on MIO pins | Cadence version r109 |
| AMD Versal™ adaptive SoC | 2x in LPD on MIO pins | Cadence version r112 |