SPI Controller I/O Signals - SPI Controller I/O Signals - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document_ID
AM011
Release_Date
2026-03-06
Revision
1.9 English

The SPI controller I/O interface is routed to both the PMC MIO pins, LPD MIO pins, and the EMIO signals.

The MIO signals are shown in the MIO-at-a-Glance Tables and all signals are detailed in the following table. The I/O signals are shown in the Functional Diagram.

Table 1. SPI Controller I/O Signals
MIO EMIO Signals (CIPS)
Signal Name I/O MIO-at-a-Glance Table Entry Input Name (I) Output Name (O) 3-state Name (O)

SPI0_SCLK
SPI1_SCLK

I/O SCLK

spi0_sclk_i

spi1_sclk_i

spi0_sclk_o

spi1_sclk_o

spi0_sclk_t

spi1_sclk_t

SPI0_MISO
SPI1_MISO

I/O MISO

spi0_io0_i

spi1_io0_i

spi0_io0_o

spi1_io0_o

spi0_io0_t

spi1_io0_t

SPI0_MOSI
SPI1_MOSI

I/O MOSI

spi0_io1_i

spi1_io1_i

spi0_io1_o

spi1_io1_o

spi0_io1_t

spi1_io1_t

SPI0_SS0_b
SPI1_SS0_b

I/O SS0

spi0_ss_i

spi1_ss_i

spi0_ss_o

spi1_ss_o

spi0_ss_t

spi1_ss_t

Manager-only Signals

SPI0_SS1_b
SPI1_SS1_b

O SS1

spi0_ss1_o_n

spi1_ss1_o_n

spi0_ss_t

spi1_ss_t

SPI0_SS2_b
SPI1_SS2_b

O SS2

spi0_ss2_o_n

spi1_ss2_o_n

spi0_ss_t

spi1_ss_t