The following table lists the RPU subsystem functional units.
| Unit | Description | Links |
|---|---|---|
| Compute Resources and Memory | ||
| RPU processor engine | Dual processor cores Cortex-R5F (Arm v7R instruction set | See RPU Processor Implementations for more processor-related functional units and Real-time Processing Unit for full descriptions |
| TCM memory | RPU tightly coupled memories: three TCMs per RPU core provides a deterministic, low-latency memory space (128 KB total per core) | Tightly-coupled Memories |
| PS manager (PSM) | PSM firmware downloaded by PLM firmware for power management of the LPD and FPD | PS Manager |
| OCM RAM | 256 KB on-chip system memory on OCM switch | On-Chip Memory |
| Accelerator RAM (XRAM) | 4 MB, four bank memory with interfaces to OCM switch and up to three PL ports | Accelerator RAM |
| LPD DMA | General purpose DMA unit with simple and linked-list functionality | LPD DMA Controller |
| Support Units | ||
| Interconnect (INT) | Switches: main, OCM, I/O peripheral, and APB | Interconnect Overview |
| OCM_XMPU | Memory protection unit for OCM port on OCM switch | Memory Protection Units |
| LPD_XPPU | Peripheral protection unit for accesses to I/O peripherals | Peripheral Protection Units |
| SWDT | System watchdog timer for software integrity monitoring | System Watchdog Timers |
| Counters | ||
| SCNTR | System counter reference for software | System Timestamp |
| I/O Peripheral Controllers | ||
| LPD GPIO | General purpose I/O controller (26 MIO channels, 32 EMIO channels) | GPIO Controller |
| GEM | Gigabit Ethernet controller | Gigabit Ethernet MAC |
| LPD_I2Cx | Two I2C controllers | I2C Controller |
| Test and Debug Resources | ||
| DBG_xx | CoreSight | – |