The QSPI_LPBK_CLK is generated from the QSPIx_CLK and routed through the output buffer to a pin and returned back through the pin's input buffer to the controller for I/O delay compensation for greater timing accuracy. During the BootROM phase of the QSPI boot flow, the BootROM runs with clock loopback (QSPI_LPBK_CLK) disabled. For the PLM phase of the QSPI boot flow, the CIPS Wizard enables the QSPI_LPBK_CLK feature by default in the PLM for all QSPIx_CLK frequencies. When the QSPI_LPBK_CLK pin feature is enabled during any phase of boot or QSPI access, the QSPI_LPBK_CLK must be routed to PMC MIO[6], and the PMC MIO[6] pin must be unconnected on the PCB. The QSPI_LPBK_CLK feature is required to be enabled when the QSPIx_CLK frequency is >37.5 MHz. The clock loopback pin can be optionally disabled in the CIPS Wizard only when the QSPIx_CLK frequency is <= 37.5 MHz.