The package integration possibilities include:
- SoC silicon die (monolithic)
- SoC silicon die with multiple super logic regions (SLR) die on a common interposer connected to the package substrate
- SoC silicon die on an interposer with a stack of high-bandwidth memory (HBM) silicon die
The SoC base die includes the PMC, PS, NoC interconnect, DDR controllers, and integrated hardware options that can include compute engines, accelerators, and peripherals. Additional stacked die will include a reduced functional PMC with the arrays of PL SLRs that serviced by the NoC Interconnect.
The integrated hardware for each device is listed in the Versal Architecture and Product Data Sheet: Overview (DS950).
SSI Technology Devices
Stacked silicon interconnect (SSI) technology combines multiple silicon dice together within a single device. Physically, SSI technology devices can be built with an interposer layer between the package substrate and two or more silicon die.
SSI technology examples include:
- HBM
- Multiple super logic regions
The following documents include content for the SoC SSI technology:
- Versal Adaptive SoC PCB Design User Guide (UG863)
- Versal Adaptive SoC System Software Developers Guide (UG1304)
The SoCs include a single die with a single PMC, a processing system, an array of programmable logic, and various integrated hardware logic.
The physical layouts are numerous, and include devices with scalable PL CFRAME arrays, optional integrated hardware accelerators and peripherals, and many different layouts that can be mirrored and modularized.
A layout with a PMC, an array of programmable logic and integrated hardware is referred to as a super logic region (SLR). The primary SLR includes a reduced-functionality PMC and a processing system.
Some devices include multiple SLRs with scalable PL layouts, integrated hardware, and I/O structures. There are monolithic designs with one or more SLRs. There are multi-die SSI technology devices with interposer layers.