PMC MIO Pin Tables - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The MIO pins programmed for a boot mode are shaded in the following tables.

Table 1. PMC MIO Pin Assignments (Bank 500)
MIO Pins: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Controllers in PMC Power Domain
OSPI Boot CLK IO 0 IO 1 IO 2 IO 3 IO 4 DS IO 5 IO 6 IO 7 CS0 CS1 RST – – – – – – – – – – – – –
QSPI 4b Boot CLK0 IO0 1 IO0 2 IO0 3 IO0 0 CS0 LPBK CS1 IO1 0 IO1 1 IO1 2 IO1 3 CLK1 – – – – – – – – – – – – –
QSPI 8b Boot CLK0 IO0 1 IO0 2 IO0 3 IO0 0 CS0 LPBK CS1 IO1 0 IO1 1 IO1 2 IO1 3 CLK1 – – – – – – – – – – – – –

SD_eMMC0
eMMC Boot

CLK
CLK

WP
–

CD
–

CMD
CMD

D 0
D 0

D 1
D 1

D 2
D 2

D 3
D 3

SEL
D 4

DIRC
D 5

DIR 0
D 6

DIR 1
D 7

PWR
RST

 – – – – – – – – – – – – –
SD_eMMC_0 – – – – – – – – – – – – – D 0 D 1 D 2 D 3 PWR CLK SEL DIRC DIR 0 DIR 1 CMD CD WP
SelectMAP – – – – – – – – – – – – – – IO 0 IO 1 IO 2 IO 3 CLK CS RW BSY IO 4 IO 5 IO 6 IO 7
Tamper Trig – – – – – – – – – – – – TRIG TRIG – – – – – – – – TRIG TRIG – –
PMC_I2C – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – –
PMC_GPIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Controllers in Low Power Domain
CAN FD 0 RX TX – – RX TX – – RX TX – – RX TX – – RX TX – – RX TX – – – –
CAN FD 1 – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX – –
LPD_I2C0 – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – –
LPD_I2C1 SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – – –
SYSMON_I2C/SMB SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – – SCL SDA SMB
PCIe resets – – – – – – – – – – – – – – – – – – – – – – – – RST0 RST1
SPI0 SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – – –
SPI1 – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – –
Trace Port – – – – CTL D 0 CLK D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 – – – –
TTC CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 – –
UART0 RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – – –
UART1 – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – –
USB 2.0 – – – – – – – – – – – – – RST D 0 D 1 D 2 D 3 CLK D 4 D 5 D 6 D 7 DIR STP NXT
LPD SWDT CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1 PEND INT WS0 WS1 – – – – – – – –
FPD SWDT – – – – – – CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1 PEND PEND WS0 WS1 – –
Note: PMC MIO pin 21 is correctly shown with route to the FPD_SWDT_RST_PEND output.
Table 2. PMC MIO (Bank 501)
MIO Pins: 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Controllers in PMC Power Domain

SD_eMMC_0
SD v3.0 Boot

 – – – – – – – – – – –

WP
–

CLK
CLK

CD
–

CMD
CMD

D 0
D 0

D 1
D 1

D 2
D 2

D 3
D 3

SEL
D 4

DIRC
D 5

DIR 0
D 6

DIR 1
D 7

PWR
RST

 – –

SD_eMMC_1
SD v2.0 Boot

CLK
CLK

DIR 1
D 7

CD
–

CMD
CMD

D 0
D 0

D 1
D 1

D 2
D 2

D 3
D 3

SEL
D 4

DIRC
D 5

DIR 0
D 6

 – – – – – – – – – – – – –

WP
–

PWR
RST

SD_eMMC_1
SD v3.0 Boot

CLK
CLK

DIR 1
D 7

CD
–

CMD
CMD

D 0
D 0

D 1
D 1

D 2
D 2

D 3
D 3

SEL
D 4

DIRC
D 5

DIR 0
D 6

 – – – – – – – – – – – – –

WP
–

PWR
RST
SelectMAP – – IO 8 IO 9 IO 10 IO 11 IO 12 IO 13 IO 14 IO 15 IO 16 IO 17 IO 18 IO 19 IO 20 IO 21 IO 22 IO 23 IO 24 IO 25 IO 26 IO 27 IO 28 IO 29 IO 30 IO 31
Tamper Trig TRIG – – – – – – – – – – TRIG – – – – – – – – – – – – TRIG TRIG
PMC_I2C SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA
PMC_GPIO 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Controllers in Low-power Domain
GEM 0 RGMII TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL – – – – – – – – – – – – – –
GEM 1 RGMII – – – – – – – – – – – – TX CLK TXD 0 TXD 1 TXD 2 TXD 3 TX CTL RX CLK RXD 0 RXD 1 RXD 2 RXD 3 RX CTL – –
GEMn MDIO – – – – – – – – – – – – – – – – – – – – – – – – CLK DATA
GEM TSU – – – – – – – – – – – – – – – – – – – – – – – – CLK CLK
CAN FD 0 RX TX – – RX TX – – RX TX – – RX TX – – RX TX – – RX TX – – – –
CAN FD 1 – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX – – TX RX – –
LPD_I2C0 SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – – –
LPD_I2C1 – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – – SCL SDA – –
SYSMON_I2C/SMB SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – SCL SDA SMB – – SCL SDA SMB – – SCL SDA SMB
PCIe Resets – – – – – – – – – – – – RST0 RST1 – – – – – – – – – – – –
SPI0 SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – – –
SPI1 – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – – – – – – SCLK CS2 CS1 CS0 MISO MOSI – –
Trace Port – – – – CTL D 0 CLK D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 – – – –
TTC CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 CLK 3 WA 3 CLK 2 WA 2 CLK 1 WA 1 CLK 0 WA 0 – –
UART0 RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – RXD TXD CTS RTS – – – – – –
UART1 – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – – – – TXD RXD RTS CTS – –
LPD SWDT CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1 PEND INT WS0 WS1 – – – – – – CLK RST1
FPD SWDT – – – – – – CLK RST PEND INT WS0 WS1 – – – – – – CLK RST PEND INT WS0 WS1 – –