The following table lists the PMC functional units.
| Unit | Description | Link |
|---|---|---|
| PMC Compute Resources | ||
| ROM code unit (RCU) | Executes BootROM code after a POR or system reset | RCU ROM Code Unit |
| Platform processing unit (PPU) | Executes platform loader and manager (PLM) firmware | PPU MicroBlaze Processor |
| PPU RAM | 384 KB memory for use by PLM | Integrated RAM Memory |
| PMC RAM | 128 KB system memory reserved for use by the PPU and its PLM firmware | Integrated RAM Memory |
| PMC DMA 0 and 1 | Streams data between secure switch and main switch | PMC DMA Units and Stream Switch |
| Support Units | ||
| IPI | Inter-processor interrupts | Inter-Processor Interrupts |
| System interrupts | System interrupts to PPU and PSM interrupt controllers | System Interrupts |
| Service request registers | Runtime service requests | |
| System EAMs | PMC and PSM error accumulator modules (EAM) | System Errors |
| Interconnect | ||
| Interconnect (INT) | Switches: main, I/O peripheral, auxiliary, and APB | Interconnect |
| PMC_XMPU | Memory protection unit (XMPU) for PMC_RAM and SBI | Memory Protection Units |
| PMC_XPPU PMC_NPI_XPPU |
Peripheral protection unit for PMC and NPI-based register modules | Peripheral Protection Units |
| APB | Register programming interface: 32-bit single read/write | APB and AXI Programming Interfaces |
| NPI | Register programming interface: 32-bit with read/write burst | NPI Programming Interface |
| Configuration | ||
| PL CFU | PL configuration frame unit | Configuration Frame Unit, CFU Controller Programming Interface |
| eFUSE controller |
Controller for eFUSE array |
– |
| eFUSE cache |
Cache of the eFUSEs |
– |
| PMC_SBI | Boot interface works with SelectMAP and JTAG data flows | |
| Supervised Boot Interfaces | ||
| JTAG TAP interface |
Serial TAG test access port controller for boundary scan and AMD opcodes |
JTAG TAP Controller |
| SelectMAP | 8, 16, or 32 bit interface | SelectMAP Boot Mode |
| SBI | Facilitates booting via SelectMAP and JTAG | SBI for JTAG and SelectMAP |
| Flash Memory Boot Interfaces | ||
| OSPI | Octal SPI 8-bit interface | OSPI Flash Boot Mode |
| QSPI | Quad SPI 4 and 8 bit interface | QSPI Flash Boot Mode |
| SD v2.0 and 3.0 | 4-bit interface | SD Flash Boot Mode |
| eMMC v4.51 | 8-bit interface | eMMC v4.51 Boot Mode |
| System Monitoring | ||
| PMC SysMon | Voltage and temperature system monitor | Versal Adaptive SoC System Monitor Architecture Manual (AM006) |
| PMC ClkMon | Clock monitor | Clock Monitor |
| Security Resources | ||
| Device security | Security management | Security Management |
| AES-GCM | Security engine for encryption and decryption | PMC AES |
| SHA3-384 | Secure hash algorithms | Secure Hash Algorithms |
| RSA/ECC | Security public-key cryptography engine with authentication algorithms | RSA/ECC |
| TRNG | True random number generator | True Random Number Generator |
| PUF | Physical unclonable function | Physically Unclonable Function |
| BBRAM | Battery-backed RAM and controller | Battery-Backed RAM |
| Timers, Counters, and RTC | ||
| RTC | Battery backup counter for time keeping | Real-Time Clock |
| I/O Peripheral Controllers | ||
| PMC GPIO | General purpose I/O controller (52 channels) | GPIO Controller |
| PMC I2C | I2C controller | I2C Controller |
| Resets and Clocks | ||
| Resets | PMC reset controller | Resets |
| Clocks | PMC clock controller | Clocks |
| Test and Debug | ||
| CoreSight™ | Software debug | CoreSight Architecture |
| Debug packet controller (DPC) | Debug packet controller; connected to the PMC main switch, JTAG, Aurora HSDP, and PL | Debug Packet Controller |
| Aurora HSDP interface | Serial high-speed debug port | Debug Packet Controller |
| JTAG TAP controller | Serial test and debug | JTAG TAP Controller |
| Arm DAP controller | Debug access port controller | Arm DAP Controller |