The PMC resets for the processors, memory, DMA and other system functional units are summarized in the following table.
Note: All reset register
control bits are active-High. A "1" means the reset is asserted.
| Functional Unit | Reset Name | Reset Register Control | Notes |
|---|---|---|---|
| Processors | |||
| RCU | RCU_RST | Miscellaneous |
Internal POR (several sources) and external, dedicated pin POR_B. |
| PPU | PPU_RST | Miscellaneous | |
| Peripherals | |||
| PMC DMA controllers | PMC_DMA_RST | DMAs connect between memory mapped PMC interconnect and the secure stream switch domain. | |
| SBI boot interface module | SBI_RST | RST_SBI [RESET] | The SBI connects the SelectMAP and JTAG boot interfaces to the secure stream switch. |
| PMC system monitor | PMC_SYSMON_RST |
|
Resets the PMC SYSMON controller including register settings and the sequencer configuration. Note: The eFUSE values are
unaffected.
|
| I/O Peripherals | |||
| PMC GPIO | PMC_GPIO_RST | RST_GPIO [RESET] | PMC GPIO peripheral controller |
| PMC I2C | PMC_I2C_RST | RST_I2C [RESET] | PMC I2C peripheral controller |
| Flash Memory Controllers | |||
| QSPI controller | QSPI_RST | RST_QSPI [RESET] | |
| OSPI controller | OSPI_RST | RST_OSPI [RESET] | |
| SD_eMMC0 controller | SD0_RST | RST_SDIO0 [RESET] | |
| SD_eMMC1 controller | SD1_RST | RST_SDIO1 [RESET] | |