The following table provides the PLL configuration register
programming values when the PLL is in integer mode.
| fbdiv | pll_cp | pll_res | pll_lfhf | lock_dly | lock_cnt |
|---|---|---|---|---|---|
| 36 - 42 | 3 | 6 | 3 | 63 | 1000 |
| 43 | 7 | 9 | 3 | 63 | 1000 |
| 44 - 49 | 3 | 10 | 3 | 63 | 1000 |
| 50 - 54 | 4 | 6 | 3 | 63 | 1000 |
| 55 | 4 | 6 | 3 | 63 | 975 |
| 56 | 6 | 1 | 3 | 63 | 950 |
| 57 - 58 | 6 | 1 | 3 | 63 | 925 |
| 59 | 6 | 1 | 3 | 63 | 900 |
| 60 | 4 | 10 | 3 | 63 | 900 |
| 61 | 4 | 10 | 3 | 63 | 875 |
| 62 | 4 | 10 | 3 | 63 | 850 |
| 63 | 5 | 6 | 3 | 63 | 850 |
| 64 - 65 | 5 | 6 | 3 | 63 | 825 |
| 65 | 5 | 6 | 3 | 63 | 825 |
| 66 - 67 | 5 | 6 | 3 | 63 | 800 |
| 68 | 5 | 6 | 3 | 63 | 775 |
| 69 | 3 | 12 | 3 | 63 | 775 |
| 70 - 72 | 3 | 12 | 3 | 63 | 750 |
| 73 - 74 | 3 | 12 | 3 | 63 | 725 |
| 75 - 77 | 3 | 12 | 3 | 63 | 700 |
| 78 - 79 | 3 | 12 | 3 | 63 | 675 |
| 81 - 83 | 3 | 12 | 3 | 63 | 650 |
| 84 - 86 | 3 | 12 | 3 | 63 | 625 |
| 87 - 89 | 3 | 12 | 3 | 63 | 600 |
| 90 - 98 | 4 | 12 | 3 | 63 | 600 |
| 99 - 114 | 3 | 2 | 3 | 63 | 600 |
| 115 - 127 | 5 | 12 | 3 | 63 | 600 |
| 128 - 138 | 4 | 2 | 3 | 63 | 600 |
| 139 - 151 | 6 | 12 | 3 | 63 | 600 |
| 152 - 158 | 5 | 2 | 3 | 63 | 600 |
| 159 - 160 | 7 | 12 | 3 | 63 | 600 |
| 161 | 5 | 2 | 3 | 63 | 600 |
| 162 - 165 | 7 | 12 | 3 | 63 | 600 |
| 166 | 5 | 2 | 3 | 63 | 600 |
| 167 - 168 | 7 | 12 | 3 | 63 | 600 |
| 169 | 5 | 2 | 3 | 63 | 600 |
| 170 - 171 | 7 | 12 | 3 | 63 | 600 |
| 171 | 7 | 12 | 3 | 63 | 600 |
| 172 - 177 | 12 | 12 | 3 | 63 | 600 |
| 178 - 180 | 6 | 2 | 3 | 63 | 600 |