PLL Clock Generator Comparisons - PLL Clock Generator Comparisons - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2026-03-06
Revision
1.9 English

MPSoC to Versal Device Comparison

The reference clock frequency dividers in the Versal device includes a single 10-bit divider. The reference clock frequency dividers in the MPSoC includes one or two 6-bit dividers.