The block RAM and UltraRAM are distributed about the SLRs. The data interface and controls are configurable.
Block RAM Features
The PL includes block RAM that can be configured and operated in different ways.
- Synchronous Operation
- Each memory access, read, and write is controlled by the clock. All inputs, data, address, clock enable, and write enable are registered. The data output is always latched, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write operation, the data output can be made to reflect the previously stored data, the newly written data, or remain unchanged. There is independent reset control of output latches and registers.
- Asynchronous Operation
- The data outputs can also be set or reset asynchronously. Sleep input (places array in low power state) can be optionally asynchronous.
- True Dual-port Operation
- The block RAM has two completely independent ports that share nothing but the stored data.
- Simple Dual-port Operation
- One port is dedicated as a write port and the other as a read port. Consequently, the data width can be extended to 72 bits for the 36 Kb full block RAM or 36 bits for the split 18 Kb block RAM.
Cascade mode supports all configurations available in 36 Kb RAM or 18 Kb RAM. Cascading refers to combining multiple block RAMs to build larger ones, without using additional logic resources.
Each 64-bit-wide block RAM can generate, store, and use eight additional bits to perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to, or reading from, external 64- or 72-bit-wide memories. To include the ECC circuitry, it must be enabled. Block RAM contents can be initialized or cleared by the configuration bitstream.
For additional features and functionality, see the Versal Adaptive SoC Memory Resources Architecture Manual (AM007).
The number of block RAMs in a device are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).
Block RAM Comparisons
The block RAM has several notable differences compared to the block RAM in the AMD UltraScale+™ device. Several features are removed, including x1, x2, x4 widths, hard FIFO (can be instantiated), address enable/compare, and systolic cascade. See the Versal Adaptive SoC Memory Resources Architecture Manual (AM007) for a complete list, including a few changes and enhancements.
UltraRAM Features
The PL includes UltraRAM that can be configured and operated in different ways.
- 32 KB of data storage, 4K x 9 bytes (64-bit data plus 8-bit ECC)
- Dual port, single-clock synchronous memory
- Cascade-able for building larger memories, dedicated column routing wires to connect adjacent UltraRAM units
- ECC on both ports with single bit error detection and correction, and double bit error detection
- Sleep power saving features
- Synchronous Operation Only
- Each memory access, read, and write is controlled by the clock. All inputs, data, address, clock enable, and write enable are registered. The data output is always latched, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
- Asynchronous Operation
- The data outputs can also be set or reset asynchronously. Sleep input (places the memory array in low-power state) can be optionally asynchronous.
- Pseudo Dual-port Operation
- There are two ports on the memory. Each port is capable of reading or writing in a single cycle. The ports are sequenced in a fixed order, allowing up to two transactions per cycle (both ports write, both ports read, or one port reads while the other writes.) This necessitates that the two ports share a common clock. During a write operation, the data output remains unchanged on a given port. There is independent reset control of output latches and registers.
The error-correction code (ECC) logic in the UltraRAM supports real time error checking and correction. Both ports have dedicated ECC for either read or write. The ECC logic is organized for 64-bit-wide data, which can generate, store, and use eight additional bits to perform single-bit error correction and double-bit error detection during the read process.
It is possible to cascade the address and data of adjacent blocks to build deeper memories. Optional pipelining is also available to maintain the clock rate through tall cascades of UltraRAM.
The number of UltraRAM blocks in a device are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).
UltraRAM Comparisons
The Versal device UltraRAM is very similar to the UltraRAM in the AMD UltraScale+™ device. There are multiple UltraRAM columns distributed in the PL. Improvements include asymmetric port widths, memory initialization values, and data cascade ordering.
For additional features and functionality, see the Versal Adaptive SoC Memory Resources Architecture Manual (AM007).