PL System Block Diagram - PL System Block Diagram - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2026-03-06
Revision
1.9 English

The PL building blocks and clock structures provide the foundation for instantiating functionality. The PL is provided with port interface signals attached to nearly every part of the device.

The high-level PL perspective of the system is shown in the following figure.

Figure 1. PL System Perspective
Figure Notes:
  1. The figure shows an example CPM. For CPM details, see the appropriate CPM product guide in the CPM section.

In addition to the PL interconnect interfaces shown in the figure, the PL port interface signals include the system interrupts, errors, events, and other signals from all parts of the device.