Overview - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The PMC includes two DMA units. Within each DMA unit are independent DMA source and DMA destination modules.

The source DMA (SRC DMA) module reads blocks of data from memory-mapped locations via its 128-bit AXI memory-mapped interface (AXI4) on the PMC AXI main interconnect switch. The SRC DMA module then writes the blocks of data to the AES, SHA, and SBI peripherals using its 128-bit streaming interface on the local PMC secure stream switch.

The destination DMA (DST DMA) module receives blocks of data from the AES, SHA, and SBI peripherals via its 128-bit streaming interface. The DST DMA module then writes the blocks of data to memory-mapped address locations via its 128-bit AXI4 interface on the PMC AXI main interconnect switch.

The SRC DMA and DST DMA modules are located side-by-side. Each module has separate register controls and separate 2-entry command queues. There is a 128-bit, 128-word data FIFO in each of these DMA modules.

The stream switch (SS) routes data between the PMC DMA units and the AES, SHA2, SHA3, and SBI. It is configured using the PMC_GLOBAL.SS_CFG register module. Any invalid configuration generates an error interrupt.