Line Control Register
The control data is written to the line control register. The LINE_CTRL register defines the:
- Transmission parameters
- Word length
- Buffer mode
- Number of transmitted stop bits
- Parity mode
- Break generation
Data Transmit and Receive
Data received or transmitted is stored in two 32-character FIFOs.
Transmit
During transmission, data is written into the transmit FIFO. When the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the LINE_CTRL register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes High as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted High while data is being transmitted. BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits.
Receive
When the receiver is idle (RXD continuously 1, in the marking state) and a Low is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter in UART mode, or the fourth cycle of the counter in SIR mode to allow for the shorter logic 0 pulses (half way through a bit period).
The start bit is valid if RXD is still Low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. When a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.
A valid stop bit is confirmed if RXD is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word.
The receive FIFO has an extra four bits per character for status information.
Clear FIFO
In addition to a controller reset, the FIFO can cleared by disabling and re-enabling it by using the LINE_CTRL [FEN] bit. Program the control registers as follows:
- Disable the UART.
- Wait for the end of transmission or reception of the current character.
- Flush the transmit FIFO by setting the [FEN] bit to [0] in the line control register, LINE_CTRL.
- Reprogram the control register, CTRL.
- Enable the UART.