OSPI SRC DMA Registers - OSPI SRC DMA Registers

OSPI SRC DMA Registers - OSPI SRC DMA Registers - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2026-03-06

Revision

1.9 English

The following table lists the DMA controller registers.

Table 1. SRC DMA Register Overview
Register Name	Offset Address	Access Type	Description
DMA_SRC_ADDR	`0x1000`	RW	Source DMA read address
DMA_SRC_Status	`0x1008`	R, WTC	Source DMA read status
DMA_SRC_CTRL1 DMA_SRC_CTRL2	`0x100C` `0x1024`	RW	Source DMA read control Reg 1 and 2
DMA_SRC_ISR DMA_SRC_IER DMA_SRC_IDR DMA_SRC_IMR	`0x1014` `0x1018` `0x101C` `0x1020`	WTC W W R	Source DMA read interrupt status, enable, disable, and mask