OSPI Flash Boot Sequences - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The BootROM runs at an OSPI device clock frequency between 11 MHz and 24.5 MHz dependent on the reference clock input frequency. During BootROM execution, the OSPI boot mode supports an 8-bit data bus width and a single data rate (SDR). The BootROM code first initiates the boot sequence with the default 4-byte address octal output fast read command code 7Ch and searches for a valid boot header. If a valid boot header is not found, the BootROM attempts to load the image using the 4-byte alternate addressing read command code 13h. If a valid boot header is still not detected, the basic read command 03h is loaded. If the boot attempt is unsuccessful after the third command, the BootROM increments the MultiBoot register ( PMC_MULTI_BOOT ) read address offset by 32 KB and tries the OSPI command sequence again to locate a valid boot header. If the OSPI boot mode search limit is reached without a successful boot, the RCU goes into lockdown and the ERROR_OUT pin is set.

The image search limit for each boot mode is listed in Boot Search Limit.

Note: After the BootROM code execution, the PLM firmware can support the double data rate (DDR) with strobe for higher performance.