UART Mode
The operation and baud rate values are controlled by the line control register, LINE_CTRL, and the baud rate divisor registers.
- Integer baud rate register, UART BAUD_INTEGER
- Fractional baud rate register, UART BAUD_FRACT
The UART generates individual, maskable interrupts:
- Receiver (including timeout)
- Transmitter
- Modem status
- Error conditions
The interrupts are OR'd together to generate the system interrupt. When a framing, parity, or break error occurs during reception, the appropriate error bit is set. When an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten.
The FIFOs can be programmed to be 1-byte deep providing a conventional double-buffered UART interface.
The modem status input signals Clear To Send (CTS), Data Carrier Detect (DCD), Data Set Ready (DSR), and Ring Indicator (RI) are supported. The output modem control lines, Request To Send (RTS), and Data Terminal Ready (DTR) are also supported.
Hardware flow control feature uses the UARTx_CTS_b input and the UARTx_RTS_b output to automatically control the serial data flow.
IrDA Mode
The serial infrared (SIR) controller contains an IrDA SIR encoder/decoder. The encoder/decoder can be enabled for serial communication through SIROUT_b and SIRIN.
When the SIR ENDEC is enabled, the UARTx_TXD line is held in the passive state (High logic level) and transitions of the modem status, or the UARTx_RXD line have no effect. The SIR encoder/decoder can receive and transmit, but it is half-duplex only, so it cannot receive while transmitting, or transmit while receiving.
The IrDA SIR physical layer specifies a minimum 10 ms delay between transmission and reception.