Message Space Data - Message Space Data

Message Space Data - Message Space Data - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2026-03-06

Revision

1.9 English

The message space includes:

The following table provides CAN FD message space register information.

Note: This memory space is implemented in RAM. After a reset, the contents are not cleared, but should be considered invalid.

Table 1. CAN FD Message Space
Name	Register Count	Access Type	Description
32 TX Buffers - ID, DLC and 16 data words
TxBuff_ID_Msg_n TxBuff_DLC_Msg_n TxBuff_DW00_Msg_n	32 32 512	RW RW RW	IDs: TxBuff_ID_Msg_{0:31}, addr step = `0x48` DLCs: TxBuff_DLC_Msg_{0:31}, addr step = `0x48` Data: TxBuff_DW{0:15}_Msg_{0:31}, step = `0x48`
32 RX Acceptance Filter - Mask and ID
AF_Mask_Reg_n AF_ID_Reg_n	32 32	RW RW	Masks: AF_Mask_Reg_{0:31}, addr step = `0x08` IDs: AF_ID_Reg_{0:31}, addr step = `0x08`
32 TX Event FIFO - ID and Data Length Codes
TxEvent_ID_Reg_n TxEvent_DLC_Reg_n	32 32	R R	IDs: TxEvent_ID_Reg_{0:31}, addr step = `0x08` DLCs: TxEvent_DLC_Reg_{0:31}, addr step = `0x08`
32 Message RX Buffer 0
RxBuff0_ID_Msg_n RxBuff0_DLC_Msg_n RxBuff0_DW00_Msg_n	64 64 1024	R R R	IDs: RxBuff0_ID_Msg_{0:63}, addr step = `0x49` DLCs: RxBuff0_ID_Msg_{0:63}, addr step = `0x48` Data: RxBuff0_DW{0:15}_Msg_{0:63}, step = `0x48`
32 Message RX Buffer 1
RxBuff1_ID_Msg_n RxBuff1_DLC_Msg_n RxBuff1_DW00_Msg_n	64 64 1024	R R R	IDs: RxBuff1_ID_Msg_{0:63}, addr step = `0x49` DLCs: RxBuff1_ID_Msg_{0:63}, addr step = `0x48` Data: RxBuff1_DW{0:15}_Msg_{0:63}, step = `0x48`