LPD DMA Implementations - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-07-28
Revision
1.8 English

The descriptor-driven, general purpose DMA unit versions are compared in the following table.

Table 1. LPD DMA Implementations
Device Generation Instances DMA Core Design Buffer Flow Control Interface
UltraScale+ MPSoC LPD and FPD AMD IP, version 1.0 LPD: 2 KB

FPD: 4 KB

 DMA2PL_CACK
Versal device LPD AMD IP 4 KB New DMA2PL_CACK flow control signal behavior
In Versal devices, the PL must not use DMA2PL_CACK in combinational logic to generate PL2DMA_CVLD because it can result in unpredictable operation. The signal is shown in PL Flow-Control Interface.
Note: The LPD DMA is a PS DMA controller that is also known as the ADMA and is implemented using the AMD ZDMA core.