The JTAG interface is used for both boot and debug functions. This includes the PMC TAP JTAG operations, Arm® DAP debug, and interfaces to the debug packet controller (DPC) for ChipScope™ solution debug. Due to this flexibility, the JTAG boot mode is popular for design bring-up and is a recommended interface for all applications.
JTAG Boot Mode Interface
The JTAG boot mode uses only dedicated I/O pins as listed in the following table.
See Test and Debug for information on the Versal device PMC TAP and Arm DAP, including supported JTAG instructions through the JTAG interface.
| Pin Name | Direction | Description |
|---|---|---|
| TDI | Input | Test data input |
| TDO | Output | Test data output |
| TMS | Input | Test mode select |
| TCK | Input | Test clock |
JTAG Boot Register Settings
During boot, the BootROM sets configuration registers that apply to each boot mode. For JTAG boot mode, the BootROM sets the registers to the initial values shown in the following table.
| Register Name | Base Address | Register Value | Description |
|---|---|---|---|
| PMC_DMA_CSR. DST_CTRL2 | 0xF11D_0824 |
0x081B_FFF8
|
PMC DMA controller 1 destination setup |
| CRP.RST_SBI | 0xF126_0324 |
0x0000_0000
|
SBI reset not asserted |
| PMC_SBI_CSR.SBI_MODE | 0xF122_0000 |
0x0000_0002
|
Device configuration mode, JTAG pass through SBI (PDI loading) |
| PMC_SBI_CSR.SBI_CTRL | 0xF122_0004 |
0x0000_0025
|
JTAG mode data transfer, SBI enabled |
| CRP.PMCPLL_CTRL | 0xF126_0040 |
0x0002_4800
|
PMC PLL (PPLL) setup uses reset defaults (REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV)) |