Each DMA channel is independent with its own register set and core interrupts. An interrupt in one channel does not affect the other channels. Each DMA channel can generate up to fifteen different interrupts, which are listed in the following table. An interrupt can indicate the completion of an operation or an error condition.
When a channel interrupt occurs, a bit is set High in its PS_DMA.ISR interrupt status register. If the corresponding interrupt mask bit is Low (enabled), a system interrupt is generated. There is a system interrupt for each of the eight DMA channels. The IRQs are listed in the System Interrupts chapter.
The fifteen DMA channel interrupts can be grouped by interrupt source
- Programming interface: address decode error on APB interface (write by software)
- Descriptor list access (read by DMA unit)
- Data memory access (read and write)
The DMA channel interrupts are listed in the table.
| Interrupt | Bit | Source | Description |
|---|---|---|---|
| INV_APB | 0 | APB programming interface | Address access error |
| SRC_DSCR_DONE | 1 | Descriptor management | Read descriptor completion |
| DST_DSCR_DONE | 2 | Descriptor management | Write descriptor completion |
| BYTE_CNT_OVRFL | 3 | DMA controller | Byte count overflow |
| IRQ_SRC_ACCT_ERR | 4 | DMA controller | Descriptor accounting done overflow on source reads |
| IRQ_DST_ACCT_ERR | 5 | DMA controller | Descriptor accounting done overflow on destination writes |
| AXI_RD_SRC_DSCR | 6 | AXI transaction | Read descriptor fetch error |
| AXI_RD_DST_DSCR | 7 | AXI transaction | Write descriptor fetch error |
| AXI_RD_DATA | 8 | AXI transaction | Read data error |
| AXI_WR_DATA | 9 | AXI transaction | Write data error |
| DMA_DONE | 10 | DMA controller | DMA done (with or without error) |
| DMA_PAUSE | 11 | DMA controller | DMA pause state |
| WRBUFF_PERR | 12 | DMA controller | RAM parity error; channel data in the common buffer |
| FREE_LIST_PERR | 13 | DMA controller | RAM parity error for list of the buffer blocks available in the common buffer |
| LINK_LIST_PERR | 14 | DMA controller | RAM parity error for managing the link list in the DMA controller |