Interrupts - AM011

Eleven maskable interrupts are generated in the UART. These are combined to produce one system interrupt that is the OR of the individual outputs. Interrupts can be enabled or disabled individually by changing the mask bits in the interrupt mask set/clear register, INTR_IMSC . Setting the appropriate mask bit High enables the interrupt.

Flow Control Interrupts

The modem status interrupt is asserted if any of the modem status signals (UARTx_CTS_b, DCD_b, DSR_b, and RI_b) change. It is cleared by writing a 1 to the corresponding bits in the interrupt clear register, INTR_CLR, depending on the modem status signals that generated the interrupt.

Transmit FIFO Level Interrupt

The transmit interrupt is asserted when one of the these events occurs:

If the FIFO is enabled and level is equal to or lower than the programmed trigger level then the transmit interrupt is asserted high. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt.
If the FIFO is disabled (have a depth of one location) and there is no data present in the transmitters single location, the transmit interrupt is asserted high. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt.

To update the transmit FIFO:

Write data to the transmit FIFO, either prior to enabling the UART and the interrupts, or after enabling the UART and interrupts.

Note: The transmit interrupt is based on a transition through a level, rather than on the level itself. When the interrupt and the UART is enabled before any data is written to the transmit FIFO the interrupt is not set. The interrupt is only set, after written data leaves the single location of the transmit FIFO and it becomes empty.

Receive FIFO Timeout Interrupt

The receive timeout interrupt is asserted when the receive FIFO is not empty and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit of the interrupt clear register, INTR_CLR.

Receive Error Interrupt

The error interrupt is asserted when an error occurs in the received data. The interrupt can be caused by a number of error conditions:

Framing
Parity
Break
Overrun

The cause of the interrupt can be determined by reading the Raw Interrupt Status register, INTR_RIS and the Masked Interrupt Status register, INTR_MIS. A raw interrupt bit can be cleared by writing to the relevant bits of the interrupt clear register, INTR_CLR (bits 7 to 10 are the error clear bits).