Interrupts Associated with PPU - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

Interrupts Generated by the PPU Processor

The PPU generates a system interrupt when the APB programming interface detects an address decode error.

GIC System Interrupt Controller

The PPU receives all system interrupts into its GIC interrupt controller. These interrupts are masked the PMC global registers. The interrupts are listed in the System Interrupts chapter.

Inter-processor Interrupts

The PPU processor is a hardwired IPI agent. This enables the PLM firmware to receive and establish communication channels between itself and other IPI processor agents. The IPI is described in Inter-Processor Interrupts.