Interrupt Masking Registers - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-07-28
Revision
1.8 English

The system interrupts are distributed to the destinations listed in the table.

Table 1. System Interrupt Masking Registers
Destination Controller ISR and IMR Programming Model
PMC GIC proxy PMC_GLOBAL PPU MicroBlaze™
PSM GIC proxy PSM_GLOBAL PSM MicroBlaze
RPU Arm® GIC-390   Arm v2 architecture
APU Arm GIC-500   Arm v3 architecture
PL Output signal None ~