The system interconnect and XRAM block diagram is shown below.
LPD OCM Switch Port Interface
There is one 128-bit AXI interface from the LPD OCM switch for access by the APU and other hosts. For this path, the memory banks are addressable from 0xFE80_0000 to 0xFEBF_FFFF (four MB).
The LPD OCM AXI interface is controlled by the LPD_INT_CSR.LPD_AXI_XRAM register.
PL AFI XRAM Interfaces
Some devices support three AXI fabric interface (AFI) channels from the PL to the XRAM crossbar switch. The PL data widths can be configured at 32, 64, 128, or 256 bits. For maximum performance, the wider PL interfaces are available.
The PL clock frequency is generally half the frequency of the LPD OCM interface. This makes the performance of the 256-bit channel equivalent to the 128-bit AXI interface for the LPD OCM channel.
The PL addresses for the XRAM...
The functionality of the XRAM AFI is based on the standard AFI FM interface as described in the with the exception of not supporting the following features:
PL Queues
Each of the three PL access ports include a read and a write queue. The depth of these FIFOs are programmable using the XRAM_SLCR.FM[0:2]_ISSUING_CAPACITY registers. The FIFO depths can be programmed for between 1 to 16 transactions.
- PL Read FIFOs
- Each of the three PL access ports include a read FIFO that supports up to 16 outstanding requests on the AXI interconnect.
- PL Write FIFOs
- Each of the three PL access ports include a write FIFO that buffers write requests.
- Reads that follow Writes
- Read requests generally get priority over writes. When a read follows a write that includes the same address and both transactions are in their FIFOs, this is detected by the bank controller. The read FIFO waits until the write is completed to the memory bank.
Crossbar Switch
The XRAM includes a 4x4 AXI crossbar switch that supports accesses from the LPD OCM switch and the three PL port interfaces to the four memory banks. Transactions from the hosts to different memory banks can occur simultaneously. The crossbar arbiter can be programmed to favor access requests from the LPD OCM switch that includes transactions from the RPU host. The pathway delay from the four host ports is the same to the four memory banks. The crossbar is a full four-way AXI switch.
- LPD OCM AXI Interface
- One 128-bit AXI interface for the LPD OCM switch provides access by the APU and other transaction hosts.
- PL AXI Interfaces
- Three AXI interfaces from the PL connect to the crossbar switch. These can be configured at 32, 64, 128, or 256 bits. These wider PL interfaces are provided because the PL clock frequency is generally half the frequency of the LPD OCM switch interface.
XMPU Protection Units
The memory protection units (XMPU) are described in the Memory Protection Units chapter. They screen for the SMID number, TZ security setting, and r/w request type.
Memory Banks
Each memory bank is one MB of data with ECC protection. The memory bank controller responds to AXI transaction requests. This includes data bursts, aligned and unaligned addresses, and partial word transactions.
Each memory bank is divided into four sub-banks; these have local low-power mode with memory retention and power islands.
ECC
The ECC bits are used to detect and correct single bit errors. It can also detect, but not correct two-bit errors. The ECC bits are associated with 64-bit data chunks. When a single-bit error is detected (always correctable), the data in the transaction is corrected, but the error is not scrubbed in memory (i.e., the corrected data is not written back to the memory bank). When an error is detected, a system interrupt and error can be generated for software to manage. The ECC bits are stored in a RAM that is separate from the data.