There are several RAM arrays integrated into the device.
PPU RAM
The PPU RAM memory is used by the platform loader and manager (PLM) firmware code and data structures. The PPU RAM is protected with ECC.
- 256 KB data
- 128 KB instruction
PMC RAM
The PMC RAM includes 128 KBs of memory protected with ECC used by the PLM to store shared data structures and other purposes.
The 128 KB PMC RAM is protected with ECC. The PMC RAM memory is used by the PLM firmware to store shared data structures and other purposes. It is accessible to any transaction host with access privileges. It is protected by the PMC_XMPU protection unit.
RPU Tightly-Coupled Memory
The tightly-coupled memory (TCM) provide predictable access latency for software running in the RPU. The TCM is divided into six banks with parallel interconnect to the processors. The TCM banks are described in the Tightly-coupled Memories.
Each RPU core includes 128 KB of tightly-coupled memory (TCM) in three banks per core. Each pair of cores can be configured as two groups for high-performance dual processor mode, or grouped together for high-safety, lock-step mode with twice the memory size (256 KB). All TCM memories are ECC protected.
The TCMs are also mapped to the 32-bit address system memory space for accessibility by other transaction hosts.
These memories are usually accessed only by the RPU processors.
On-chip Memory
All devices include on-chip RAM memory that is located on the LPD OCM switch. The OCM is described in the On-Chip Memory chapter.
Accelerator RAM Memory
The accelerator RAM (XRAM) device option includes an AXI interface port from the LPD OCM switch and up to three AXI interface ports from the PL, depending on device. Refer to Accelerator RAM chapter for more information.