IPI Registers

The IPI registers include the following. Access to the registers are controlled by the LPD_XPPU protection unit and the IPI itself.

APB_MISC_xxx: Interrupt status and control (ISR non-lockable)
APB_ERR_CTRL: Programming interface access error control
SAFETY_CHK: Safety check ( non-lockable)
PROT_CTRL: Protection control
ERR_STATUSxxx: Transaction error address (non-lockable)
SMID_xx: System management ID profiles
LOCK: Register access lock (once set, stays set until POR reset)
ECC_xxx: First failing address, data and ECC register access with correctable/uncorrectable error
APER_TZ_xxx: Source agent message buffer TrustZone security access settings
xxx_TRIG, xxx_OBS, xxx_ISR, xxx_IER, xxx_IDR: Interrupt control and status for the agents

Access to the registers are controlled by the LPD_XPPU protection unit and the IPI (see Versal Adaptive SoC Register Reference (AM012)).

Agent Interrupt Registers

The IPI interrupt registers have access restriction based on the processor's SMID and security settings in the APER_TZ registers.

The IPI processor interrupt management registers are not affected by the IPI register LOCK control register.

Each agent interrupt is managed by a set of six registers:

TRIG trigger register is a write only
OBS observation register is read only
ISR interrupt status register is read and W1C
IMR interrupt mask registers is read only
IER interrupt enable register is write only
IDR interrupt disable register is write only

The IPI control registers are summarized in the following table.

Table 1. IPI Control Registers
Register Name	Access Type	Lockable	Description
APB_CTRL	RW	Yes	APB programming interface address decode error signal enable
APB_MISC_ISR APB_MISC_IMR APB_MISC_IER APB_MISC_IDR	R, W1C R W W	All except ISR	Access violation and ECC error interrupt status, mask, enable and disable
SAFETY_CHK	RW	No	Safety check registers
PROT_CTRL	RW	Yes	Enable permission checking, parity error checking, and error response
ERR_STATUS1_LO ERR_STATUS1_HI ERR_STATUS2	R	No	Address and ID of error transaction
SMID_00 SMID_01 SMID_02 SMID_03	R	Yes	SMID identification for: PSM read/write PSM read-only PMC read/write PMC read-only
SMID_04 SMID_05 etc. SMID_19	RW	Yes	System management identification for software defined sources
LOCK	RWSO	NA	Locks write access to all IPI registers except the ISR
IPI_ECC_CTRL	RW	Yes	ECC control
IPI_ECC_CE_FFA IPI_ECC_CE_FFD IPI_CE_FFE	R	Yes	First failing address, data and ECC register access with correctable error
IPI_ECC_UE_FFA IPI_ECC_UE_FFD IPI_UE_FFE	R	Yes	First failing address, data and ECC register access with un-correctable error
IPI_FI_CNTR IPI_FI_D IPI_FI_S		Yes	Fault injection count, data, and syndrome
IPI_APER_TZ_000 IPI_APER_TZ_001 IPI_APER_TZ_002 IPI_APER_TZ_003 IPI_APER_TZ_004 IPI_APER_TZ_005 IPI_APER_TZ_006 IPI_APER_TZ_007 IPI_APER_TZ_008	RW	Yes	Source agent message buffer TrustZone security access settings: 0: secure access required 1: non-secure

Register Write Lock Bit

The IPI registers can only be configured by a TrustZone secure transaction. The secure transaction is routed through the LPD_XPPU protection unit to make sure the transaction host has access privileges before it is allowed to reach the IPI programming interface with its additional restrictions.

Writes to the IPI registers can be blocked by setting the LOCK [ReqWrDis] lock bit = 1. Once this bit is set, it can only be cleared by a POR.

After the lock bit is set, many of the registers can no longer be written to until a POR occurs.

IPI Registers - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Agent Interrupt Registers

Register Write Lock Bit