IPI Controller Implementations - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The following tables show the comparisons of the IPI controller implementations.

Table 1. IPI Controller Implementations, Part A
Device Generation Register Programming Interface Protection Register 32B Boundary Message Buffer Protection Number of Agents
UltraScale+ MPSoC XPPU provides protection for 0xFF30_0000 Single 32-bit transfers only XPPU provides protection for 0xFF99_0000 Nine
Versal device IPI provides protection for 0xFF30_0000 Burst access within aligned 32B address range IPI provides its own message protection for 0xFF3F_0000 Nine (eight with message buffer and 1 without buffer)
Table 2. IPI Controller Implementations, Part B
Device Generation Message buffer programming Permission setting RAM Implementation Lock feature
UltraScale+ MPSoC Fully programmable and in software control XPPU has permission RAM entries for 128x 32B apertures Data and ECC in one RAM module Not present
Versal device Read/write access hard-coded Permissions are hard-coded in hardware Data and ECC in one RAM module Lock feature added