- Set the transfer direction as read and clear the FIFOs. Write
41h
to the Control register. - Clear the interrupts. Read and write back the read value of the IRS status register.
- Write the read data count to the transfer size register and hold
bus, if required. Write the read data count value to the Transfer_Size register.
If the read data count is greater than the FIFO depth, set Control [HOLD] =
1
. - Write the slave address. Write the address to the Address register.
- Wait for data to be received into the FIFO. Poll on Status [RXDV]
=
1
.- If Status [RXDV] =
0
, and any of the following interrupts are set: Interrupt_Status [NACK], Interrupt_Status [ARB_LOST], Interrupt_Status [RX_OVF], or Interrupt_Status [RX_UNF], then stop the transfer and report the error, otherwise continue to poll on the Status [RXDV]. - If Status [RXDV] =
1
, and if any of the following interrupts are set: Interrupt_Status [NACK], Interrupt_Status [ARB_LOST], Interrupt_Status [RX_OVF], or Interrupt_Status [RX_UNF], then stop the transfer and report the error. Otherwise, go to step 6.
- If Status [RXDV] =
- Read the data and update the count. Read the data from the FIFO
until Status [RXDV] =
1
. Decrement the read data count and if it is less than or equal to the FIFO depth, clear the Control [HOLD] register. - Check for the completion of transfer. If the total read count
reaches zero, poll on Interrupt_Status [COMP] =
1
. Otherwise, continue from step 5.