I/O Interfaces - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The controller provides I/O signals for two I/O interface paths:

  • RGMII to the LPD MIO pins

RGMII Interface

The controller includes a GMII to RGMII adapter. The RGMII I/O interface is multiplexed through the LPD MIO for connection to an external PHY. This interface supports the 10/100/1000 Mbps protocol. See the RGMII Interface Signals via MIO section.

MDIO to External PHY for RGMII

To support the external PHY for the RGMII interface, the controller includes a management data input/output (MDIO) interface. The MDIO interface includes clock, data, and output enable signals that are routed from the controller to LPD MIO pins. See MDIO Interface Signals section.

Internal Loopback

The controller has an internal loopback from the TXD to RXD signals in the GMII/MII controller.

  • Ethernet loopback connecting TXD to RXD within a controller using the Network_Control [loopback_local] register bit.

In MAC internal loopback mode, both transmit and receive clock are sourced from the GEM_REF_CLK from the LPD clock controller.

Important: Receive and transmit must be disabled when making the switch into and out of internal loopback because the clocks provided might glitch while switching to the loopback reference clock.