I/O Buffer Pin Banks - I/O Buffer Pin Banks - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2026-03-06
Revision: 1.9 English

The following table lists the I/O buffer pin banks.

Table 1. PMC, PS, and Other I/O Buffer Pin Banks
Bank Name	Pin Count	Buffer Type	Description
PMC DIO Bank	15	Digital	Dedicated I/O with POR_B, REF_CLK, JTAG, and boot mode.
PMC DIO_A Bank	4	Analog	Dedicated I/O with POR_B, REF_CLK, JTAG, and boot mode.
PMC MIO Bank 0 PMC MIO Bank 1	52	Digital	Multiplexed I/O for boot devices and peripherals in the PMC and LPD IOPs. See Multiplexed I/O Signal Pins and Output Buffer Control Registers.
LPD MIO Bank	26	Digital
PL X5IO	32 per bank	X5IO IOB	The X5IO pins are grouped in banks of 32 IOBs (16 pairs) with each IOB having direct access to the X5IO PHY logic which is used for the integrated DDRMC, soft memory controllers, MIPI (C-PHY and D-PHY) and custom high-performance I/O interfaces. The X5IO are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) with the layout described in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
PL XPIO	54 per bank	XP IOB	The XPIO pins are grouped into banks of 54 IOBs (27 I/O pairs) with each IOB having associated XP IOL logic and shared XPHY logic. The XPIO can be used with the integrated DDRMC or are available for use as I/O for the PL, except for the XPIO banks located in the corners of the die. The XPIO are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) with the layout described in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
PL HDIO	Varies	Digital	Multiple banks of HDIO buffers connect PL to device pins. The HDIO IOL and IOB resources are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
GTY or GTYP	Varies	Transceiver	The GTY/GTYP transceivers in the Versal architecture are power-efficient transceivers, supporting line rates from 1.25 Gb/s to 32.75 Gb/s. For more details, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
GTM	Varies	Transceiver	The GTM transceiver in the Versal architecture is a power-efficient transceiver, supporting line rates between 9.5 Gb/s and 112 Gb/s. For more details, see the Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017) .
GTM2	Varies	Transceiver	The GTM2 transceiver in the Versal architecture is a power-efficient transceiver, supporting line rates between 1.25 Gb/s and 112.84 Gb/s. For more details, see the Versal Adaptive SoC GTM2 Transceivers Architecture Manual (AM031).