GPIO Registers - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The two GPIO controllers have two registers sets: PMC_GPIO and LPD_GPIO. There are a total of 174 channels. There are 4 sets of GPIO registers in the PMC. These are numbered:

  • 0 and 1 for MIO
  • 3 and 4 for EMIO

There are three sets of GPIO registers in the LPD. These are numbered:

  • 0 for MIO
  • 3 and 4 for EMIO
Note: All APB programmable interfaces require single 32-bit read and write transactions. Software should perform a read-modify-write to all registers that include a reserved or an unknown bit field.
Table 1. GPIO Register Overview
GPIO Registers Access Type Description
Data Read and Write

MASK_DATA_x_LSW

 R/W This register enables more selective changes to the desired output value. Any combination of up to 16 bits can be written. Those bits that are not written are unchanged and hold their previous value. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. This register avoids the need for a read-modify-write sequence for unchanged bits.
MASK_DATA_x_MSW R/W This register is the same as MASK_DATA_LSW, except it controls the upper 16 channels of the bank.
DATA_x R/W This register controls the value to be output when the GPIO signal is configured as an output. All 32 bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}, and does not return the current value on the device pin.
DATA_x_RO R

For MIOs, this register always returns the state of the GPIO MIO pin. If the GPIO is configured as an output, this normally reflects the value being driven on the output regardless of the DIRM_x setting.

Note: If the MIO is not configured for this pin as a GPIO, the DATA_RO returns unpredictable results.
I/O Buffer Control
DIRM_x R/W

Direction mode controls whether the I/O pin is acting as an input or an output. This must be set to input to detect an interrupt and be routed to the DATA_RO register.

  • 0: enable I/O as an input for the interrupt detector and data register
  • 1: enable I/O as an output from the status/mask registers
OEN_x R/W

When the I/O is configured as an output, the OEN controls whether the output is enabled (OEN = 1) or in tristate mode (OEN = 1).

Note: There are overriding tristate control registers in the PMC_IOP_SLCR and LPD_IOP_SLCR register sets. If a bit in the MIO_MST_TRIn register is set = 1, the output buffer is put in a tristate mode regardless of the state of the OEN signal state from the GPIO controller.
Interrupt Control
INT_MASK_x R INT_MASK masks the latched INT_STAT value. To generate an interrupt:
  • INT_MASK must = 0 (enable interrupt)
  • INT_STAT must = 1 (active interrupt)
INT_EN_x W Write 1 to enable the interrupt; sets the INT_MASK bit = 0.
INT_DIS_x W Write 1 to disable the interrupt; set the INT_MASK bit = 1.
INT_STAT_x W1C Indicates if an interrupt event occurred, latched before INT_MASK.
INT_TYPE_x R/W INT_TYPE is programmed by software to set level (0) or edge (1) sensitivity.
INT_POLARITY_x R/W INT_POLARITY selects between active-Low/falling (0) and active-High/rising (1) sensitivity.
INT_ANY_x R/W INT_ANY selects single edge sensitivity defined by INT_POLARITY (0) or either edge event (1).