Functional units are summarized in implementation tables that are included in various chapters of the TRM. These tables are located under the features section of the chapters. These tables list the implementation of processors, controllers, interfaces, peripherals, integrated RAMs, and other functional units for each device generation.
The SoC generations include:
- AMD Zynq™ UltraScale+™ MPSoCs
- Versal devices
The functional units are listed in the following sections:
Platform Boot, Control, and Status Implementations (Section III)
and DMA (Section VI)
Embedded Processor, Configuration, and Security Implementations (Section VII)
Interconnect Implementations (Section VIII)
Interconnect includes AXI switches, system memory management unit (SMMU), APU cache coherent interconnect, memory protection units (XPPU, XMPU), and system watchdog timer (SWDT) units.
System Interrupts and Errors Implementations (Section IX)
Timers, Counters, and RTC Implementations (Section X)
Controllers, Integrated RAMs, and Storage Registers Implementations (Section XI)
I/O Peripheral Controller Implementations (Section XII)
Flash Memory Controller Implementations (Section XIII)
Clocks, Resets, and Power Implementations (Section XIV)
Test and Debug (Section XV)
NoC, DDR, and other Integrated Hardware
The functionality of the NoC interconnect, DDR memory, PL, and the integrated hardware is described in other documents. The instances of the integrated hardware for a particular device are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).