The following table lists the flash memory controller clock frequency requirements.
| Controller and Mode | Description |
|---|---|
| Quad-SPI Controller Interface, see the QSPI Clocks section | |
| Single, non-manual mode | PMC_IRO_CLK > 3/15 * QSPI_REF_CLK |
| Dual stacked, non-manual mode | PMC_IRO_CLK > 3/31 * QSPI_REF_CLK |
| Dual parallel, non-manual mode | PMC_IRO_CLK > 3/7 * QSPI_REF_CLK |
| Quad-SPI Controller Mode | |
| Manual mode, CPOL=1 and CPHA=1 |
QSPI_REF_CLK ≥ PMC_LSBUS_CLK |
| All modes with QSPIx_CLK frequency > 37.5 MHz |
QSPI_REF_CLK > 2 * QSPIx_CLK |
| Octal-SPI Controller | |
| DLL mode |
OSPI_CLK = OSPI_REF_CLK |
| Non-DLL mode |
OSPI_CLK ≤ OSPI_REF_CLK / 4 |
| SD_eMMC Controller, see the SD Clocks section | |
| DLL mode |
SD_DLL_REF_CLK ≥ 6 * SDx_REF_CLK Note: This requires setting the DLL divider to 6
(reset value) or greater.
|
|
Source these clocks from the same PLL |
|