Each GPIO channel can be dynamically programmed on an individual or bank basis.
- Enable, bit or bank data write, output enable and direction
controls
- Enable 3-state output
- Write output logic level
- Direction control
- Programmable interrupts on individual GPIO basis
- Raw status read and masked interrupt
- Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (rising, falling, or both)
- Two methods to write output logic levels:
- Full-bank write using the DATA_x registers
- Maskable-bit write on half-bank basis using the MASK_DATA_x_{LWS, MWS} registers
- Simultaneous output switching is possible with one register write
- Input logic levels are read one bank at a time using the DATA_RO_x registers