The PS APU is a dual-core processor that is based on the Arm superscalar, out-of-order execution Arm Cortex-A72 core.
The 64-bit Cortex-A72 cores are based on Arm-v8A architecture that supports hardware virtualization. Each A72 core includes:
- 48 KB of L1 instruction cache with parity protection
- 32 KB of L1 data cache with ECC protection
- NEON SIMD pipeline
- Floating point unit (FPU): single and double precision
- Embedded trace microcell (ETM) to support real-time debug and trace. The ETM communicates with the Arm CoreSight™ debug system.
The APU is located in the FPD. The APU is clocked independently from the FPD blocks and can be reset independently or with the FPD power domain.
CPU Pipelines
Caches
The architecture supports hardware virtualization. Each Cortex-A72 processor includes a 48-KB L1 instruction cache with parity protection and a 32 KB L1 data cache with ECC protection.
The processors have a built-in two-stage MMU that supports multi-threading and multi-operating system applications. Processors and DMA units in all parts of the system can potentially participate in the APU L2 cache coherency address space by routing their transactions through the system memory management unit (SMMU) via its translation buffer units (TBU) that are connected to the CCI in the FPD. The SMMU maps the virtual addresses to the shared physical address space in main memory.
Power islands include:
- Each processor core can be enabled and disabled individually using its own power island
- L2 cache power island
Interrupt Controller
The processor also includes the GIC-500 interrupt controller with its GIC v3 architecture.
Test and Debug
To support real-time debug and trace, each processor has an embedded trace macrocell (ETM) that communicates with the Arm CoreSight™ debug system.