The PPU and PSM processors generate a 32-bit address. The other sources of transactions can generate the extended addresses. Some do this with a base address register appended to their 32-bit address generation.
Transactions include several attributes that are used by the interconnect and the destination, including:
- Single or burst data transfers
- Secure or non-secure TrustZone declaration
- System management identification (SMID)
- 32-bit address transaction hosts:
- PPU running PLM firmware
- PSM running PSM firmware
- RPU processors
- Extended-bit address transaction hosts:
- APU, LPD_DMA, PL and others
- 44-bit physical address
- 48-bit virtual address
- Physical addresses are routed to the NoC, DDR memory, PL and other memory-mapped destinations
- Virtual addresses are routed for shared, cacheable memory to the FPD SMMU and memory coherent interconnect
- Quality of service (QoS) traffic types
The transaction attributes are explained in the Transaction Hosts and Their Attributes chapter. The parameter values used by each initiator are listed in Interconnect Interface Protocols chapter.
iPort Interfaces
The iPort interface receives transactions in to the interconnect switch and provides several functions:
- Monitors the transaction to make sure it adheres to protocol
- Assigns the TrustZone security state for the source
- Generates data parity for writes
- Checks data parity for reads
- Supports isolation that will quiesce the interface
ePort Interfaces
The ePort interface dispatches the transaction out from the interconnect switch to the destination, and provides several functions:
- Monitors the transaction for switch timeout
- Checks data parity for writes
- Generates data parity for reads
- Supports isolation that will quiesce the interface
Between the iPorts and ePorts there can be a protection unit within the interconnect switch.