Features - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English
  • 32-character deep transmit FIFO (8-bit wide)
  • 32-character deep receive FIFO (12-bit wide)
  • Standard asynchronous communication bits (start, stop and parity)
  • Independent interrupt masking:
    • Transmit and receive FIFOs
    • Receive timeout, modem status, and error condition
  • False start bit detection
  • Line break generation and detection
  • Modem control functions CTS, DCD, DSR, RTS, DTR, and RI
  • APB programming interface include address decode and parity checking

Programmable Parameters

  • Programmable hardware flow control
  • Fully-programmable serial interface characteristics
    • 5, 6, 7, or 8-bit data character
    • Even, odd, stick, or no-parity bit generation and detection
    • 1 or 2 stop bits can be generated
    • Baud rate generator; DC up to UARTx_REF_CLK / 16
  • Communication baud rate, integer, and fractional parts
  • RX and TX FIFOs can be enabled (32-character deep) or disabled (1-character deep)
  • RX and TX FIFO trigger levels are individually selectable: 1/8, 1/4, 1/2, 3/4, and 7/8

Modem Operation

The UART can be used to support the data terminal equipment (DTE) and the data communication equipment (DCE) modes of operation.