- Hardware-based memory coherency between ACE hosts (APU L2-cache and PL system cache)
- I/O coherency with ACE-Lite connected hosts
- Crossbar interconnect functionality between sources and destinations
- Snoop filter (SF) with entry table to improve performance for snoop table misses
- DVM message transport between processors for communication between MMUs
- Quality of service (QoS) features for traffic management
- Data striping is supported on the four AXI interfaces to the NoC
- Performance monitoring unit (PMU) to count performance-related events
- Support for Arm TrustZone technology to provide secure, non-secure, and protected states
- Programmer registers to control coherency and interconnect functionality
The CCI supports secure and non-secure operations that can be used within a system that uses Arm TrustZone to provide secure, non-secure, and protected states. The CCI also supports cache maintenance operations and exclusive accesses.
The PMU provides events and counters that indicate CCI runtime performance. PMU registers are in the FPD_CCI_CORE register module and provide information on the status of the interconnect. These registers can be used for system debug. See the Arm CoreLink CCI-500 Cache Coherent Interconnect Technical Reference Manual, section 2.4 for more information.
In addition, the CCI provides a set of QoS regulation and control mechanisms. For this and additional functionality, see the Arm CoreLink CCI-500 Cache Coherent Interconnect Technical Reference Manual, section 2.4 for more information.