- Selectable clock input:
- Internal PS bus clock based on the APB interface (IOP_REF_CLK)
- Internal clock (from PL)
- External clock (from MIO)
- Three independent 32-bit timer/counters
- 16-bit prescaler for the clock
- Three system interrupts, one for each timer counter
- Interrupt on overflow and counter match programmable values is generated as a system interrupt
- Increment and decrement counting
- Generate a waveform output (for example, PWM) through the MIO and to the PL
Operating Modes
Each of the timer counters can operate in one of these modes:
- Interval timing mode (increment and decrement count)
- Overflow detection mode (increment and decrement count)
- Event timer mode
The register matching interrupt can be enabled in each of these modes.
Reset State
After reset, the TTC counters are set to this configuration:
- Overflow mode
- Internal clock selected
- Counter disabled
- All interrupts disabled
- Event timer disabled
- Output waveforms disabled
System Perspective
All four of the TTC controllers are located in the LPD subsystem.