There are many integrated component and peripheral options in the Versal adaptive SoC that are summarized in the Versal Architecture and Product Data Sheet: Overview (DS950) based on device series and device within a series.
The SoC hardware architecture interconnect diagram is shown in the following figure.
Figure 1. Device-level Interconnect Architecture
Figure Notes:
- The figure shows an example CPM, connectivity, and GT transceiver interface. For CPM, connectivity, and GT transceiver interface details, see the appropriate CPM product guide in the CPM section.
- See the Control, Interface and Processing System LogiCORE IP Product Guide (PG352) or Processing System Wizard LogiCORE IP Product Guide (PG450) for PMC and PS configuration wizard details.