The DDR memory controller is designed for high efficiency and low latency to support general purpose CPUs following the AXI4 standard, as well as other traditional FPGA applications like video, network buffering, etc.
DDR4 Memory Controller
The integrated DDR 4 memory controller (DDRMC) is attached to the NoC interconnect. The controller supports both the DDR4 and LPDDR4 memory interfaces. It can be configured with a 32-bit or 64-bit DDR data interface with or without ECC. Some devices include multiple DDR memory controllers. The DDRMC has four NoC interface ports to handle multiple streams of traffic and supports quality of service (QoS) classes to ensure appropriate prioritization of the memory requests inside the controller.
Each DDRMC also includes a memory protection unit (XMPU) to only allow authorized accesses by specific transactions with proper security and read/write attributes.
For more information on the integrated DDRMC, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
DDR5 Enhanced Memory Controller
Each SoC device can have multiple DDR5 memory controllers (DDRMC5). The number of memory controllers in a device is specified in the Versal Architecture and Product Data Sheet: Overview (DS950).
The SoC device includes one or more LP/DDR5 enhanced memory controllers (DDRMC5E) to provide high efficiency and low latency support for the PS processors and traditional FPGA applications like video, network buffering, etc.
Full-memory encryption is supported with AES-GCM and AES-XTS.
A built-in hardware masking feature is available when using AES-GCM or AES-XTS encryption to provide resistance to DPA or SCA. The DDRMC5E controller also includes these features:
- Higher bandwidth
- FUSA requirements and features
- Enhanced calibration features