The DDR memory controller is designed for high efficiency and low latency to support general purpose CPUs following the AXI4 standard, as well as other traditional FPGA applications like video, network buffering, etc.
DDR4 Memory Controller
The integrated DDR 4 memory controller (DDRMC) is attached to the NoC interconnect. The controller supports both the DDR4 and LPDDR4 memory interfaces. It can be configured with a 32-bit or 64-bit DDR data interface with or without ECC. Some devices include multiple DDR memory controllers. The DDRMC has four NoC interface ports to handle multiple streams of traffic and supports quality of service (QoS) classes to ensure appropriate prioritization of the memory requests inside the controller.
Each DDRMC also includes a memory protection unit (XMPU) to only allow authorized accesses by specific transactions with proper security and read/write attributes.
For more information on the integrated DDRMC, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
DDR5 Memory Controller
Some SoC devices can have multiple DDR5 memory controllers (DDRMC5C or DDRMC5E). The number of DDR5 memory controllers in a device is specified in the Versal Architecture and Product Data Sheet: Overview (DS950).
The DDR5 memory controllers support memory encryption with AES-GCM and AES-XTS. The DDRMC5E memory controller supports AES-GCM with hardware masking and keyrolling and AES-XTS with keyrolling.
For more information about DDR5 memory controllers, see Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)