The controller has three reset domains.
- Controller wrapper
- Controller core
- External ULPI PHY
Reset Matrix
The controller receives one reset input from the SoC and several local register-controlled resets. These are summarized in the following table.
| Description | Register Control | Controller Wrapper | Controller Core | External ULPI PHY 1 |
|---|---|---|---|---|
| USB_RESET | USB_CORE_RST | USB_ULPI_RST | ||
| Controller reset | CRL.RST_USB [RESET] | Yes | Yes | Yes |
| Core soft reset | USB_XHCI.GCTL [CORESOFTRESET] | Yes | Yes | Yes |
| Internal logic | USB_XHCI.USB_CMD [HCRST] | Yes | Yes | Yes |
| Core soft reset | USB_XHCI.DCTL [CSFTRST] | Yes | Yes | Yes |
| Light host reset | USB_XHCI.USB_CMD [LHCRST] | ~ | Yes | ~ |
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